IDT89HPES24N3A1ZCBXG IDT, Integrated Device Technology Inc, IDT89HPES24N3A1ZCBXG Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
IDT89HPES24N3A1ZCBXG
Manufacturer Part Number
IDT89HPES24N3A1ZCBXG
Description
IC PCI SW 24LANE 3PORT 420-SBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT89HPES24N3A1ZCBX8.pdf
(31 pages)
Specifications of IDT89HPES24N3A1ZCBXG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89HPES24N3A1ZCBXG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT89HPES24N3A1ZCBXG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT89HPES24N3A1ZCBXG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
System Clock Parameters
AC Timing Characteristics
IDT 89HPES24N3A Data Sheet
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Refclk
Refclk
T
V
T
R
1.
2.
3.
4.
PCIe Transmit
UI
T
T
MAX-JITTER
T
T
T
IDLE
T
DATA
T
PCIe Receive
UI
T
R
jitter
SW
T
Parameter
TX-EYE
TX-EYE-MEDIAN-to-
TX-RISE
TX- IDLE-MIN
TX-IDLE-SET-TO-
TX-IDLE-TO-DIFF-
TX-SKEW
RX-EYE (with jitter)
, T
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
AC coupling required.
Parameter
F
FREQ
DC
2
, T
TX-FALL
Input reference clock frequency range
Duty cycle of input clock
Rise/Fall time of input clocks
Differential input voltage swing
Input clock jitter (cycle-to-cycle)
Termination Resistor
Unit Interval
Minimum Tx Eye Width
Maximum time between the jitter median and maximum
deviation from the median
D+ / D- Tx output rise/fall time
Minimum time in idle
Maximum time to transition to a valid Idle after sending
an Idle ordered set
Maximum time to transition from valid idle to diff data
Transmitter data skew between any 2 lanes
Unit Interval
Minimum Receiver Eye Width (jitter tolerance)
Description
Description
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
4
Table 9 Input Clock Requirements
10 of 31
Min
399.88
399.88
Min
100
0.6
0.7
0.4
40
50
50
1
Typical
Typical
400
500
400
110
90
50
.9
1
0.2*RCUI
Max
400.12
400.12
Max
1300
0.15
125
125
20
20
1.6
60
1
1
Units
April 23, 2008
RCUI
Unit
Ohms
MHz
ps
ps
ps
UI
UI
UI
UI
UI
ps
UI
ps
%
V
3