IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 53
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IDT72V51556L7-5BB8
Manufacturer Part Number
IDT72V51556L7-5BB8
Description
IC FLOW CTRL MULTI QUEUE 256-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT72V51546L7-5BB8.pdf
(58 pages)
Specifications of IDT72V51556L7-5BB8
Configuration
Dual
Density
2Mb
Access Time (max)
4ns
Word Size
36b
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.6V
Supply Current
100mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V51556L7-5BB8
JTAG INTERFACE
support the JTAG boundary scan interface. The IDT72V51546/72V51556
incorporates the necessary tap controller and modified pad cells to implement
the JTAG facility.
program files for these devices.
TEST ACCESS PORT (TAP)
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
Note that IDT provides appropriate Boundary Scan Description Language
The Tap interface is a general-purpose port that provides access to the
TDO
TDI
TMS
TCLK
TRST
T
A
P
Cont-
roller
TAP
clkDR, ShiftDR
clklR, ShiftlR
UpdatelR
Figure 33. Boundary Scan Architecture
UpdateDR
Instruction Register
Control Signals
53
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
The Standard JTAG interface consists of four basic elements:
• • • • •
• • • • •
• • • • •
• • • • •
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture
The Tap controller is a synchronous finite state machine that responds to
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Instruction Decode
Mux
5904 drw36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES