IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 8

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

PIN DESCRIPTIONS (CONTINUED)
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
FSTR
(R4)
FSYNC
(R3)
FXI
(T2)
FXO
(T3)
ID[2:0]
(ID2-C9
ID1-A10
ID0-B10)
IW
(L15)
MAST
(K15)
MRS
(T9)
OE
(M14)
Symbol &
Pin No.
(1)
(1)
(1)
PAFn Flag Bus
Strobe
PAFn Bus Sync
PAFn Bus
Expansion In
PAFn Bus
Expansion Out
Device ID Pins
Input Width
Master Device
Master Reset
Output Enable
Name
OUTPUT during Polled operation of the PAFn bus. During Polled operation each quadrant of queue status flags
OUTPUT PAFn bus operation has been selected . FXO of device ‘N’ connects directly to FXI of device ‘N+1’. This
I/O TYPE
INPUT
INPUT
LVTTL
INPUT
LVTTL
LVTTL
INPUT
LVTTL
LVTTL
LVTTL
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The
If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK
and the WRADD bus to select a quadrant of queues to be placed on to the PAFn bus outputs. A quadrant
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus
selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus
is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads
quadrant 1 on to PAFn, the second WCLK rising edge loads quadrant 2 and so on. The fifth WCLK rising
edge will again load quadrant 1. During the WCLK cycle that quadrant 1 of a selected device is placed
on to the PAFn bus, the FSYNC output will be HIGH. For all other quadrants of that device, the FSYNC
output will be LOW.
The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn
bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a token from the previous device in a chain. In single device mode the FXI input must be tied
LOW if the PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI input
must be connected to the FXO output of the same device. In expansion mode the FXI of the first device
should be tied LOW, when direct mode is selected.
FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
pin pulses when device N has placed its final (4th) quadrant on to the PAFn bus with respect to WCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising
edge the first quadrant of device N+1 will be loaded on to the PAFn bus. This continues through the chain
and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of each device
in the chain provides synchronization to the user of this looping event.
For the 32Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue
selection takes place the 3 MSb’s of this 8 bit address bus are used to address the specific device (the
5 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s
of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is ‘111’, however the ID does not have to match the device order. In single device mode these pins should
be setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The
ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
This pin is used in conjunction with OW and BM to setup the input and output bus widths to be a combination
of x9, x18 or x36, (providing that one port is x36).
The state of this input at Master Reset determines whether a given device (within a chain of devices), is the
master device is the first to take control of all outputs after a master reset, all slave devices go to
High-Impedance, preventing bus contention. If a multi-queue device is being used in single device mode,
this pin must be set HIGH.
A master reset is performed by taking MRS from HIGH to LOW, to HIGH. Device programming is required
after master reset.
The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
in High Impedance until that device has been selected on the Read Port, at which point OE provides three-
state of that respective device.
8
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES