IDT72V51436L7-5BBI IDT, Integrated Device Technology Inc, IDT72V51436L7-5BBI Datasheet - Page 19

• Manufacturer Part Number: IDT72V51436L7-5BBI
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51436L7-5BBI

• Configuration: Dual
• Density: 512Kb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51436L7-5BBI

TABLE 2 — READ ADDRESS BUS, RDADD[7:0]
READ QUEUE SELECTION AND READ OPERATION (STANDARD MODE)
vices can be configured up to a maximum of 16 queues which data can be read
via a common read port using the data outputs (Qout), read clock (RCLK) and
read enable (REN). An output enable, OE control pin is also provided to allow
High-Impedance selection of the Qout data outputs. The multi-queue device
read port operates in a mode similar to “First Word Fall Through” on a
SuperSync IDT FIFO, but with the added feature of data output pipelining (see
Figure 10, Write Operations & First Word Fall Through). The queue to be
read is selected by the address presented on the read address bus (RDADD)
during a rising edge on RCLK while read address enable (RADEN) is HIGH.
The state of REN does not impact the queue selection. The queue selection
is requires 2 RCLK cycles. All subsequent data reads will be from this queue
until another queue is selected.
the device as opposed to Packet Mode where complete packets may be read.
The read port is designed such that 100% bus utilization can be obtained. This
means that data can be read out of the device on every RCLK rising edge
including the cycle that a new queue is being addressed.
(see Figure 12, Read Queue Select, Read Operation). RADEN goes high
signaling a change of queue (clock cycle “D”). The address on RDADD at that
time determines the next queue. Data presented during that cycle (“D”) will be
read at “D” (+ t
is active LOW. If REN is HIGH (inactive) for this clock cycle, data will not be read
from the previous queue. The next cycle’s rising edge (“E”), the read port
discrete empty flag will update to show the empty status of the newly selected
queue (Q
word from the previous (old) queue (Q
IDT72V51436/72V51446/72V51456 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
The IDT72V51436/72V51446/72V51456 multi-queue flow-control de-
Standard mode operation is defined as individual words will be read from
Changing queues requires a minimum of two RCLK cycles on the read port
F
). The internal pipeline is also loaded at this time (“D”) with the last
A
), can be read from the active (old) queue (Q
Read Queue
PAEn/PRn
Operation RCLK
Sector
Select
Select
P
) as well as the next word from the new
RADEN
P
), provided REN
1
0
Address
Sector
0
1
ESTR
0
1
19
Q0 : Q7 → PAE0 : PAE7
Q8 : Q15 → PAE0 : PAE7
queue (Q
the OE is asserted) consecutively (cycles “E” and “F” respectively) following
the selection of the new queue regardless of the state of REN, unless the new
queue (Q
queue will be prevented. Data cannot be read from an empty queue. The last
word in the data output register (from the previous queue), will remain on the
data bus, but the output valid flag, OV will go HIGH, to indicate that the data
present is no longer valid. This pipelining effect provides the user with 100%
bus utilization, and brings about the possibility that a “NULL” queue may be
required within a multi-queue device. Null queue operation is discussed in the
next section. Remember that OE allows the user to place the data output bus
(Qout) into High-Impedance and the data can be read in to the output register
regardless of OE.
12, 14, and 15 for read queue selection and read port operation timing
diagrams.
PACKET MODE OPERATION (PKT = HIGH on Master Reset)
packets or frames can be written to the device as opposed to Standard mode
where individual words are written. For clarification, in Packet Mode, a packet
can be written to the device with the starting location designated as Transmit
Start of Packet (TSOP) and the ending location designated as Transmit End
of Packet (TEOP). In conjunction, a packet read from the device will be
designated as Receive Start of Packet (RSOP) and a Receive End of Packet
(REOP). The minimum size for a packet is four words (SOP, two words of data
and EOP). The almost empty flag bus becomes the “Packet Ready” PR flag
bus when the device is configured for packet mode. Valid packets are indicated
when both PR and OV are asserted.
Refer to Table 2, for Read Address Bus arrangement. Also, refer to Figures
The Packet mode operation provides the capability where, user defined
Device Select
(Compared to
ID0,1,2)
Device Select
(Compared to
ID0,1,2)
7 6 5
Queue Status on PAEn/PRn Bus
F
F
). Both of these words will fall through to the output register( provided
) is empty. If the newly selected queue is empty, any reads from that
RDADD[7:0]
Null-Q
Select
4
4 3 2 1
X X X
Pin
Read Queue Address
(4 bits = 16 Queues)
3 2 1 0
X
Address
Sector
COMMERCIAL AND INDUSTRIAL
0
5935 drw06
TEMPERATURE RANGES