IDT72V51543L7-5BB IDT, Integrated Device Technology Inc, IDT72V51543L7-5BB Datasheet - Page 17

• Manufacturer Part Number: IDT72V51543L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51543L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51543L7-5BB

TABLE 1 — WRITE ADDRESS BUS, WRADD[7:0]
required for the device to load its internal setup registers. When a single multi-
queue is used, the completion of device programming is signaled by the SENO
output of a device going from HIGH to LOW. Note, that SENI must be held LOW
when a device is setup for default programming mode.
the first device in a chain can be held LOW. The SENO of a device should connect
to the SENI of the next device in the chain. The SENO of the final device is used
to indicate that default programming of all devices is complete. When the final
SENO goes LOW normal operations may begin. Again, all devices will be
programmed with their maximum number of queues and the memory divided
equally between them. Please refer to Figure 8, Default Programming.
WRITE QUEUE SELECTION & WRITE OPERATION
32 queues that data can be written into via a common write port using the data
inputs, Din, write clock, WCLK and write enable, WEN. The queue address
present on the write address bus, WRADD during a rising edge on WCLK while
write address enable, WADEN is HIGH, is the queue selected for write
operations. The state of WEN is don’t care during the write queue selection cycle.
The queue selection only has to be made on a single WCLK cycle, this will remain
the selected queue until another queue is selected, the selected queue is always
the last queue selected.
This means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed. When a new queue
is selected for write operations the address for that queue must be present on
the WRADD bus during a rising edge of WCLK provided that WADEN is HIGH.
IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
When multi-queue devices are connected in expansion mode, the SENI of
The IDT72V51543/72V51553 multi-queue flow-control devices have up to
The write port is designed such that 100% bus utilization can be obtained.
PAFn Quadrant
Write Queue
Operation WCLK WADEN
Select
Select
1
0
Quadrant
Address
17
00
01
10
11
A queue to be written to need only be selected on a single rising edge of WCLK.
All subsequent writes will be written to that queue until a new queue is selected.
A minimum of 2 WCLK cycles must occur between queue selections on the write
port. On the next WCLK rising edge the write port discrete full flag will update
to show the full status of the newly selected queue. On the second rising edge
of WCLK, data present on the data input bus, Din can be written into the newly
selected queue provided that WEN is LOW and the new queue is not full. The
cycle of the queue selection and the next cycle will continue to write data present
on the data input bus, Din into the previous queue provided that WEN is active
LOW.
in to the previous queue.
queue will be prevented, a full queue cannot be written into.
The least significant 5 bits are used to address one of the 32 available queues
within a single multi-queue device. The most significant 3 bits are used when
a device is connected in expansion mode, up to 8 devices can be connected
in expansion, each device having its own 3 bit address. The selected device
is the one for which the address matches a 3 bit ID code, which is statically setup
on the ID pins, ID0, ID1, and ID2 of each individual device.
bus strobe), to address the almost full flag bus quadrant during direct mode of
operation.
9, Write Queue Select, Write Operation and Full flag Operation and Figure
11, Full Flag Timing Expansion Mode for timing diagrams.
If WEN is HIGH, inactive for these 2 clock cycles, then data will not be written
If the newly selected queue is full at the point of its selection, then writes to that
In the 32 queue multi-queue device the WRADD address bus is 8 bits wide.
Note, the WRADD bus is also used in conjunction with FSTR (almost full flag
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
FSTR
0
1
Queue Status on PAFn Bus
Q0 : Q7 → PAF0 : PAF7
Q8 : Q15 → PAF0 : PAF7
Q16 : Q23 → PAF0 : PAF7
Q24 : Q31 → PAF0 : PAF7
Device Select
(Compared to
ID0,1,2)
Device Select
(Compared to
ID0,1,2)
7 6 5
7 6 5
WRADD[7:0]
Write Queue Address
(5 bits = 32 Queues)
4 3 2
4 3 2
X
X
COMMERCIAL AND INDUSTRIAL
X Quadrant
Address
TEMPERATURE RANGES
1 0
1 0
5938 drw05