IDT72V51543L7-5BB IDT, Integrated Device Technology Inc, IDT72V51543L7-5BB Datasheet - Page 18

• Manufacturer Part Number: IDT72V51543L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51543L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51543L7-5BB

TABLE 2 — READ ADDRESS BUS, RDADD[7:0]
READ QUEUE SELECTION & READ OPERATION
from via a common read port using the data outputs, Qout, read clock, RCLK
and read enable, REN. An output enable, OE control pin is also provided to allow
High-Impedance selection of the Qout data outputs. The multi-queue device
read port operates in a mode similar to “First Word Fall Through” on a traditional
IDT FIFO, but with the added feature of data output pipelining. This data
pipelining on the output port allows the user to achieve 100% bus utilization,
which is the ability to read out a data word on every rising edge of RCLK
regardless of whether a new queue is being selected for read operations.
edge on RCLK while read address enable, RADEN is HIGH, is the queue
selected for read operations. A queue to be read from need only be selected
on a single rising edge of RCLK. All subsequent reads will be read from that
queue until a new queue is selected. A minimum of 2 RCLK cycles must occur
between queue selections on the read port. Data from the newly selected queue
will be present on the Qout outputs after 2 RCLK cycles plus an access time,
provided that OE is active, LOW. On the same RCLK rising edge that the new
queue is selected, data can still be read from the previously selected queue,
provided that REN is LOW, active and the previous queue is not empty on the
following rising edge of RCLK a word will be read from the previously selected
queue regardless of REN due to the fall through operation, (provided the queue
is not empty). Remember that OE allows the user to place the Qout, data output
bus into High-Impedance and the data can be read onto the output register
regardless of OE.
queue (provided that the queue is not empty), will fall through to the output
IDT72V51543/72V51553 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
The multi-queue flow-control device has up to 32 queues that data is read
The queue address present on the read address bus, RDADD during a rising
When a queue is selected on the read port, the next word available in that
Read Queue
Quadrant
Operation RCLK
Select
Select
PAEn
RADEN
1
0
Quadrant
Address
00
01
10
11
ESTR
18
0
1
register after 2 RCLK cycles. As mentioned, in the previous 2 RCLK cycles to
the new data being available, data can still be read from the previous queue,
provided that the queue is not empty. At the point of queue selection, the 2-stage
internal data pipeline is loaded with the last word from the previous queue and
the next word from the new queue, both these words will fall through to the output
register consecutively upon selection of the new queue. This pipelining effect
provides the user with 100% bus utilization, but brings about the possibility that
a “NULL” queue may be required within a multi-queue device. Null queue
operation is discussed in the next section on.
on the same RCLK edge and the following RCLK edge, 2 final reads will be made
from the previous queue, provided that REN is active, LOW. On the next RCLK
rising edge a read from the new queue will not occur, because the queue is
empty. The last word in the data output register (from the previous queue), will
remain there, but the output valid flag, OV will go HIGH, to indicate that the data
present is no longer valid.
bus strobe), to address the almost empty flag bus quadrant during direct mode
of operation. In the 32 queue multi-queue device the RDADD address bus is
8 bits wide. The least significant 5 bits are used to address one of the 32 available
queues within a single multi-queue device. The most significant 3 bits are used
when a device is connected in expansion mode, up to 8 devices can be
connected in expansion, each device having its own 3 bit address. The selected
device is the one for which the address matches a 3 bit ID code, which is statically
setup on the ID pins, ID0, ID1, and ID2 of each individual device.
12,14 & 15 for read queue selection and read port operation timing diagrams.
Queue Status on PAEn Bus
Q0 : Q7 → PAE0 : PAE7
Q8 : Q15 → PAE0 : PAE7
Q16 : Q23 → PAE0 : PAE7
Q24 : Q31 → PAE0 : PAE7
If an empty queue is selected for read operations on the rising edge of RCLK,
The RDADD bus is also used in conjunction with ESTR (almost empty flag
Refer to Table 2, for Read Address bus arrangement. Also, refer to Figures
Device Select
(Compared to
ID0,1,2)
Device Select
(Compared to
ID0,1,2)
7 6 5
7 6 5
RDADD[7:0]
Read Queue Address
(5 bits = 32 Queues)
4 3 2
4 3 2
X
X
X Quadrant
Address
COMMERCIAL AND INDUSTRIAL
1 0
1 0
5938 drw06
TEMPERATURE RANGES