IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 11

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

IDT77V400
1.
2.
device characterization, but is not production tested
3.
edge to prevent initiating another Reset operation.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ICLK frequency must not exceed SCLK frequency.
Transition is measured +/-200mV from Low or High impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by
Although RESET is an asynchronous function, it must be centered around the SCLK so that it will be Low 10ns prior to the next SCLK rising
HC
SCM
HCM
SIO
HIO
CDIO
DCIO
CYCI
CHI
CLI
SIF
HIF
SID
HID
OE
OHZ
OLZ
RST
RSTL
CTEN
CTHZ
CTLZ
CDCR
DCCR
CYCO
CHO
CLO
SOF
HOF
CDOF
CDOF
CDOD
DCOD
CKHZ
CKLZ
Symbol
1
CS Hold Time after SCLK High
CMD Setup Time to SCLK High
CMD Hold Time after SCLK High
IOD Setup Time to SCLK High
IOD Hold Time after SCLK High
SCLK to IOD Valid
IOD Output Hold after SCLK High
ICLK Cycle Time
ICLK High Time
ICLK Low Time
IFRM Setup Time to ICLK High
IFRM Hold Time after ICLK High
ID Setup Time to ICLK High
ID Hold Time after ICLK High
OE Low to Data Valid
OE High to Output High-Z
OE Low to Output Low-Z
RESET High Pulse Width
RESET Low to SCLK High
CTLEN Low to Data Valid
CTLEN High to Output High-Z
CTLEN Low to Output Low-Z
SCLK to CRCERR Valid (1 cycle delay)
CRCERR Output Hold after SCLK High
OCLK Cycle
OCLK High Time
OCLK Low Time
OFRM Setup Time to OCLK High
OFRM Hold Time after OCLK High
OCLK to OFRM Valid
OFRM Output Hold after OCLK High
OCLK to OPxD Valid
OD Output Hold after OCLK High
SCLK High to Output High-Z
SCLK High to Output Low-Z
Parameter
2
3
2
2
2
2
2
11 of 26
Min.
1
4
1
4
1
—
2
23
9
9
4
1
4
1
—
—
2
20
10
—
—
2
—
2
23
9
9
4
1
—
2
—
2
—
2
77V400S156 Com’l & Ind
Max.
—
—
—
—
—
18
—
—
—
—
—
—
—
—
15
15
—
—
—
15
15
—
18
—
—
—
—
—
—
18
—
18
—
15
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
March 31, 2001