IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 13

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

Control Interface Commands
Control Interface Commands
Control Interface Commands
Control Interface Commands
Control Interface Timing Waveform
Control Interface Timing Waveform
Control Interface Timing Waveform
Control Interface Timing Waveform
1
2
IDT77V400
All output signals except CRCERR are controlled by OE.
The 13-bit cell address, 4-bit selected Switching Memory address, and the 5-bit Edit Buffer Protect and Clear control bits are valid at this time.
CTLEN is Low and the CTLEN bit of the configuration register (Bit 31) is LOW for this waveform.
CRCERR
IOD0-31
SCLK
CMD0-5
GPIx
GHIx
GPE
GHE
GST
GER
STEx
STIx
LDOx
PPE
PHE
PHEC
REF
LDC
OPE
OHE
OHEC
NOP
Command
CS
1.
2.
3.
OE
CMD bus commands not defined in this table are undefined and not to be implemented.
"x" represents the specific ISAM or OSAM being accessed (IP0-IP7 or OP0-OP7 respectively).
"n" represents the appropriate bit of the binary representation of the ISAM or OSAM being accessed (000 to 111).
1
t
SCM
t
SC
STATUS
GET
1
t
HC
t
HCM
t
CH
Get Pre/Post Pend Data from ISAMx
Get Header from ISAMx
Get Pre/Post Pend Data from Edit Buffer
Get Header from Edit Buffer
Get ISAM and OSAM Status Register Bits
Get Error Register Bits
Store Cell in ISAMx
Store Cell in ISAMx
Load Cell from Memory into OSAMx
Put new Pre/Post Pend in Input Edit Buffer
Put new Header in Input Edit Buffer
Put new Header and new CRC byte in Input Edit Buffer
Refresh Memory
Load Configuration Register
Put Pre/Post Pend Data in Output Edit Register
Put new Header in Output Edit Register
Put new Header and new CRC byte in Output Edit Register
No Operation
t
CYC
t
CL
NOP
Command Description
2
2
t
SCM
and Input Edit Buffer in Memory
in Memory
HEADER
t
OLZ
GET
2
t
OE
t
HCM
t
CDIO
Old Header
2
2
Output -
STORE
13 of 26
ISAM
t
DCIO
t
CDCR
Cell Addr
HEADER
[ CRC ERROR = LOW ]
Input -
PUT
2
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
COMMAND Bus Bit (CMD5:0)
STATUS
New Header
MSb
GET
Input -
5
t
CDIO
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
4
[ AVAILABLE FOR NEXT COMMAND ]
0
1
0
0
0
0
0
1
0
1
1
1
0
1
1
1
1
1
3
Output -
Status
t
DCIO
n
n
0
1
0
1
n
n
n
0
1
1
1
0
0
1
0
1
2
3
3
3
3
3
n
n
0
0
1
1
n
n
n
0
0
0
1
1
1
1
0
1
1
3
3
3
3
3
t
OHZ
n
n
0
0
0
0
n
n
n
0
0
1
1
0
1
0
1
1
LSb
3
3
3
3
3
0
3606 drw 07
March 31, 2001