IDT88P8341BHGI IDT, Integrated Device Technology Inc, IDT88P8341BHGI Datasheet - Page 15

• Manufacturer Part Number: IDT88P8341BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8341BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8341BHGI

3.1.2 SPI-3 egress
of EOP fragment which may be shorter
LID to LP map
Multiple burst enable
Poll length
from [0 up to POLL_LENGTH] to find logical ports that can accept data
Loopback enable
interface for test purposes
Data memory egress control
out of the data memory. The function of the SPI-3 egress port descriptor table
(block_base 0x1700) is to define where data goes after exiting the main data
memory. There are four options configurable:
Maximum number of memory segments
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
- 64 entries, one per LID, for each SPI-3 egress port
- LP enable control
- Allows more than one burst to be sent to an LP.
- For use when in Link mode and when using the packet level mode
- Causes polling of the PHY for the logical ports associated to LIDs ranging
- Range is 0-63
- Enables loopback from SPI-3 physical interface to same SPI-3 physical
The SPI-3 egress port descriptor table (block_base 0x1700) for both paths
- SPI-3
- SPI-4
- Capture
- Discard
- Defines the largest BUFFER available to a LP / LID
- Each segment is 256 bytes
- Range 1 – 508 in increments of one segment
- All fragments will be of a programmable equal length with the exception
15
SPI-3 egress interface configuration
successive transfers.
supported as opposed to the one defined by the SPI-3 implementation
agreement.
register.
the PACKET flag in the SPI-3 general configuration register.
the E_PRTY signal as defined by the EVEN flag in the Table 50, SPI-3 general
configuration register (register_offset=0x00).
the STX signal. The option is enabled by the STX_SPACING flag in the Table
50, SPI-3 general configuration register (register_offset=0x00).
an EOP signal. The option is enabled by the EOP_SPACING flag in the Table
50, SPI-3 general configuration register (register_offset=0x00).
SPI-3 egress interface errors
cycle period. The result of this process is reported in the E_FCLK_AV flag in
Table 58, SPI-3 egress fill level register (Block_base 0x0700 +
Register_offset=0x03).
generates a maskable SPI-3 egress clock unavailable interrupt indication,
SPI3_ECLK_UN, in Table 62-Non LID associated interrupt indication register
(Block_Base 0x0C00 + Register_offset 0x0C).
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A clock available process detects an E_FCLK cycle within a 64 MCLK clock
A status change from the clock available status to the clock not available status
SPI Exchange allows for a pause at least two cycles of E_FCLK between
SPI Exchange allows for over clocking for a higher clock frequency
The Link mode is selected by the Link flag in the SPI-3 general configuration
The interface operates in PACKET mode or BYTE mode as defined by
SPI Exchange generates even or odd parity over E_DATA[7/31:0] on
SPI Exchange optionally generates two dummy cycles after assertion of
SPI Exchange optionally generates two dummy cycles after assertion of
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006