IDT88P8341BHGI IDT, Integrated Device Technology Inc, IDT88P8341BHGI Datasheet - Page 64

• Manufacturer Part Number: IDT88P8341BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8341BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8341BHGI

9.3.11 Block base 0x1600 registers
SPI-4 ingress packet length configuration
(Block_base 0x1600 + Register_offset 0x00-0x3F)
TABLE 79 - SPI-4 INGRESS PACKET LENGTH
CONFIGURATION (64 ENTRIES CONFIGURABLE)
associated with the SPI-3 interface. The register has read and write access. The
minimum and maximum packet lengths per LID are provisioned using the SPI-
4 ingress packet length configuration register. The bit fields of a SPI-4 ingress
packet length configuration register are described.
packet length is programmed from 0 to 255 bytes. The resolution is one byte.
packet length is programmed from 0 to 16,383 bytes. The resolution is one byte.
9.3.12 Block base 0x1700 registers
SPI-3 egress port descriptor table (Block_base
0x1700 + Register_offset 0x00-0x3F)
TABLE 80 - SPI-3 EGRESS PORT DESCRIPTOR
TABLE (64 ENTRIES)
The SPI-3 egress port descriptor table has read and write access. The SPI-
3 egress per LID packet fragment length and direction are provisioned using
the SPI-3 egress port descriptor tables. The bit fields of the SPI-3 egress port
descriptor table are described.
more than MAX_BURST field multiplied by sixteen is the packet fragment length
for the LP. For example, programming the number 3 into the MAX_BURST field
results in a packet fragment length of (3+1) x 16 = 64 bytes. The MAX_BURST
field is used to prioritize traffic.
The Path selection is defined for each of the 64 LIDs by the associated
DIRECTION field as shown in the following table.
TABLE 81 - SPI-3 EGRESS DIRECTION CODE
ASSIGNMENT
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
MIN_LENGTH
Reserved
MAX_LENGTH
The SPI-4 ingress registers are at Block_base 0x1600.
There is oneset of 64 registers for SPI-4 ingress packet length configuration
MIN_LENGTH SPI-4 ingress minimum packet length. The minimum
MAX_LENGTH SPI-4 ingress maximum packet length. The maximum
There are 64 SPI-3 egress port descriptor tables for the SPI-3 egress port.
MAX_BURST
DIRECTION
DIRECTION
MAX_BURST
Reserved
DIRECTION
Reserved
00
01
10
11
Field
Field
SPI-3 packet fragment length for a SPI-3 egress LP. One
The SPI-3 egress traffic is directed to a SPI-3 egress port.
SPI-3 physical
Reserved
Capture
Discard
29:16
31:10
Bits
15:8
Bits
7:0
3:0
7:4
8:9
Path
Length
Length
14
22
8
8
4
4
2
Initial Value
Initial Value
0x5EE
0x40
0x0
0x0F
0b11
0x00
0x0
64
9.3.13 Block base 0x1800 registers
SPI-4 ingress port descriptor table (Block_base
0x1800 + Register_offset 0x00-0x3F)
TABLE 82 - SPI-4 INGRESS PORT DESCRIPTOR
TABLES (64 ENTRIES)
3 interface. The SPI-4 ingress port descriptor tables are 32 bits wide and have
read and write access. Each of the SPI-4 ingress port descriptor tables is used
to control the amount of buffering and the backpressure threshold of the available
buffer segment pool for the SPI-4 ingress.
segments of 256 bytes per segment. The 508 buffer segments can be shared
among the LIDs initially programmed by the numerical field NR_LID. Of the share
of the buffer memory, a SPI-4 LID can be allocated the maximum number of
segments permitted, or can be programmed to fewer segments by decreasing
the M field. Decreasing M increases the chance of backpressure and possibly
buffer overflow, but can result in lower latency.
(hungry threshold) fields are used, along with the M field, to set the two
backpressure settings per LID on the SPI-4 ingress. The FREE_SEGMENT_S
field must always be greater than the FREE_SEGMENT_H field.
range of M is 0x000 to 0x1FC (508 base 10), but can not exceed the number
dictated by NR_LID [Block_base 0x1900 + Register_offset 0x00].
threshold based on the number of free buffer pool segments (M) available, as
follows:
defined as:
threshold based on the number of free buffer pool segments (M) available, as
follows:
defined for FREE_SEGEMENT_S.
M
Reserved
FREE_SEGMENT_S
Reserved
FREE_SEGMENT_H
Reserved
There is one set of 64 registers for SPI-4 ingress port descriptors for the SPI-
Each SPI-4 ingress buffer segment pool is 128 Kbytes, divided into 508 buffer
The FREE_SEGMENT_S (starving threshold) and FREE_SEGMENT_H
M
FREE_SEGMENT_S
This field is used to define the SPI-4 ingress per-LID starving backpressure
THRESHOLD_S = N * FREE_SEGEMENT_S, where the value of N is
FREE_SEGMENT_H
This field is used to define the SPI-4 ingress per-LID hungry backpressure
THRESHOLD_H = N * FREE_SEGEMENT_H, where the value of N is as
Field
The number of 256-byte buffer pool segments allocated to a LID. The
0x1FF to 0x100
0x0FF to 0x080
0x07F to 0x040
0x03F to 0x020
0x01F to 0x000
M[8:0]
20:16
23:21
28:24
31:29
Bits
15:9
8:0
INDUSTRIAL TEMPERATURE RANGE
Length
9
7
5
3
5
3
16
N
8
4
2
1
Initial Value
APRIL 10, 2006
0x000
0x00
0x00
0x00
0x0
0x0