IDT72T55258L6-7BBI IDT, Integrated Device Technology Inc, IDT72T55258L6-7BBI Datasheet - Page 29

• Manufacturer Part Number: IDT72T55258L6-7BBI
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55258L6-7BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55258L6-7BBI

corresponding read clock, read enable, and read chip select. A data word will
be read on the rising (and falling in DDR) edge of read clock provided read
enable and read chip select are active. There are also four individual output
enables that will take the output bus to high-impedance. Note that data will be
read from memory regardless of the state of the output enable OE[3:0] pins.
As explained above, in FWFT mode the first word written to each Queue will
automatically be placed onto the output bus regardless of the of the state of the
corresponding read enable. There is a two cycle input pipeline and a two cycle
output pipeline. It will take two cycles or three rising edges of the WCLK to move
data from the write port to the queue and two cycles or those rising edges of
RCLK to move data from the queue to the data outlines.
BROADCAST WRITE MODE
Write mode block diagram on page 2. The device in this mode consists of four
separate Queues: Queue 0, Queue 1, Queue 2 and Queue 3. The four Queues
all have one common write port which will write data into all four Queues
simultaneously when a write operation is initiated, there is no write selection
to write data into a specific Queue. The Broadcast Write mode can be used in
applications where a single incoming data bus needs to be sent to multiple data
paths simultaneously.
WRITE PORT OPERATION
individual Queues separately. The write port will write data into all four Queues
simultaneously. Note that in Broadcast mode only the WCLK0 is active, all other
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
In Broadcast Write mode the device is configured as shown in the Broadcast
In Broadcast Write mode there are no input or output select pins to select the
29
input clocks are not used. The same applies to the write enable (WEN0) and
write chip select (WCS0). Data will be written on the rising (and falling in DDR)
edge of write clock provided write enable and write chip select are active (LOW)
on the rising edge of write clock. Write operations are prohibited if any of the
four Queues are being partially reset or any of their full flag status full (FF =
LOW).
be placed onto the output bus of that respective Queue regardless of the state
of the corresponding read enable, provided that the selected Queue was empty
and its corresponding output ready flag was inactive. There is a two cycle input
pipeline and a two cycle output pipeline. It will take two cycles or three rising
edges of the WCLK to move data from the write port to the queue and two cycles
or those rising edges of RCLK to move data from the queue to the data outlines.
This occurs due to the nature of the FWFT flag timing. Subsequent writes to
the Queue that is not empty will not fall through to the output bus. In IDT Standard
mode, every word including the first word must be accessed by the read enable
and read chip select.
READ PORT OPERATION
each individual Queue. Data can be read from any of the four Queues using
its corresponding read clock, read enable, and read chip select. A data word
will be read on the rising (and falling in DDR) edge of read clock provided read
enable and read chip select are active. There are also four individual output
enables that will take the output bus to high-impedance. Note that data will be
read from memory regardless of the state of the output enable OE[3:0] pins.
In FWFT mode, the first word written to a selected Queue will automatically
In Broadcast Write mode there are four independent read port controls for
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009