IDT72T55258L6-7BBI IDT, Integrated Device Technology Inc, IDT72T55258L6-7BBI Datasheet - Page 34

• Manufacturer Part Number: IDT72T55258L6-7BBI
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55258L6-7BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55258L6-7BBI

Queue will go HIGH with respect to WCLK, when the maximum number of words
has been written into the Queue, thus inhibiting further write operations. Upon
the completion of a valid read cycle, the input ready flag will go LOW with respect
to WCLK two cycles later, thus allowing another write to occur, provided t
has been met.
COMPOSITE FULL/INPUT READY FLAG (CFF/CIR)
The composite full/input ready flag represents the state of the Queue selected
on the write port, such that the user does not have to monitor each individual
Queues’ full/input ready flags. The composite full/input ready flag is only
available in both Demux and Broadcast modes. When switching from one
Queue to another, the composite full/input ready flag will update to the status of
the newly selected Queue one WCLK cycle after the rising edge of WCLK that
made the new Queue selection, regardless of which timing mode the device is
operating in. See Figure 28, Composite Full Flag for the relevant associated
timing diagram. See Table 3 and 4 “Status Flags for IDT Standard and FWFT
Mode “ for the truth table of the composite full flag
PROGRAMMABLE ALMOST EMPTY FLAG (PAE0/1/2/3)
each corresponding to the individual Queues in memory. The programmable
almost empty flag is an additional status flag that notifies the user when the Queue
is near empty. The user may utilize this feature as an early indicator as to when
the Queue will become empty. In IDT Standard mode, PAE will go LOW when
there are n words or less in the Queue. In FWFT mode, the PAE will go LOW
when there are n-1 words or less in the Queue. The offset “n” is the empty offset
value. The default setting for this value is stated in Table 2. Since there are four
internal Queues hence four PAE offset values, n0, n1, n2, and n3.
of the Programmable Flag Mode (PFM) pin during master reset. If PFM is tied
HIGH, then synchronous timing mode is selected. If PFM is tied LOW, then
asynchronous timing mode is selected. In synchronous PAE configuration, the
PAE flag is updated on the rising edge of RCLK. In asynchronous PAE
configuration, the PAE flag is asserted LOW on the LOW-to-HIGH transitions of
the Read Clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transitions
of the Write Clock (WCLK). See Figure 36, and 38, Synchronous and
Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and
FWFT mode), for the relevant timing information.
another.
PROGRAMMABLE ALMOST FULL FLAG (PAF0/1/2/3)
corresponding to the individual Queues in memory. The programmable almost
full flag is an additional status flag that notifies the user when the Queue is nearly
full. The user may utilize this feature as an early indicator as to when the Queue
will not be able to accept any more data and thus prevent data from being
dropped. In IDT Standard mode, if no reads are performed after master reset,
PAF will go LOW after (D-m) (D meaning the density of the particular device)
words are written to the Queue. In FWFT mode, PAF will go LOW after (D+1-
m) words are written to the Queue. The offset “m” is the full offset value. The default
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
To prevent data overflow in the FWFT mode, the input ready flag of each
This status pin is used to determine the full state of the current Queue selected.
There are four programmable almost empty flags available in this device,
There are two timing modes available for the PAE flags, selectable by the state
The four programmable almost empty flags operate independent of one
There are four programmable almost full flags available in this device, each
SKEW
34
setting for this value is stated in Table 2. Since there are four internal Queues
hence four PAF offset values, m0, m1, m2, and m3.
of the Programmable Flag Mode (PFM) pin during master reset. If PFM is tied
HIGH, then synchronous timing mode is selected. If PFM is tied LOW, then
asynchronous timing mode is selected. In synchronous PAF configuration, the
PAF flag is updated on the rising edge of WCLK. In asynchronous PAF
configuration, the PAF flag is asserted LOW on the LOW-to-HIGH transitions
of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH
transitions of the Read Clock (RCLK). See Figures 35 and 37, Synchronous
and Asynchronous Programmable Almost-Full Flag Timing (IDT Standard
and FWFT mode), for the relevant timing information.
another.
TABLE 6 — T
Configuration
DDR Output
DDR Output
There are two timing modes available for the PAF flags, selectable by the state
The four programmable almost full flags operate independent of one
SDR Output
SDR Output
DDR Input
DDR Input
SDR Input
SDR Input
Data Port
to
to
to
to
Status Flags
EF/OR
EF/OR
EF/OR
EF/OR
FF/IR
FF/IR
FF/IR
FF/IR
PAE
PAF
PAE
PAF
PAE
PAF
PAE
PAF
SKEW
Negative Edge WCLK to
Negative Edge RCLK to
Negative Edge WCLK to
Negative Edge RCLK to
Negative Edge WCLK to
Negative Edge WCLK to
Negative Edge RCLK to
Negative Edge RCLK to
Positive Edge WCLK to
Positive Edge WCLK to
Positive Edge WCLK to
Positive Edge WCLK to
Positive Edge RCLK to
Positive Edge RCLK to
Positive Edge RCLK to
Positive Edge RCLK to
T
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge WCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
Positive Edge RCLK
SKEW
MEASUREMENT
COMMERCIAL AND INDUSTRIAL
Measurement
TEMPERATURE RANGES
FEBRUARY 01, 2009
Parameter
Datasheet
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SKEW2
SKEW2
SKEW3
SKEW3
SKEW2
SKEW1
SKEW3
SKEW3
SKEW1
SKEW2
SKEW3
SKEW3
SKEW1
SKEW1
SKEW3
SKEW3