IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet

IDT72T55268L5BB

Manufacturer Part Number

IDT72T55268L5BB

Description

IC CTRL QUADMUX FLOW 324-BGA

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT72T55248L6-7BB.pdf (65 pages)

Specifications of IDT72T55268L5BB

Configuration

Dual

Density

4.5Mb

Access Time (max)

3.6ns

Word Size

36b

Sync/async

Synchronous

Expandable

Yes

Bus Direction

Uni-Directional

Package Type

BGA

Clock Freq (max)

200MHz

Operating Supply Voltage (typ)

2.5V

Operating Supply Voltage (min)

2.375V

Operating Supply Voltage (max)

2.625V

Supply Current

150mA

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

324

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

72T55268L5BB

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FEATURES

• • • • •

FUNCTIONAL BLOCK DIAGRAMS

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Choose from among the following memory organizations:

IDT72T55248 - 8,192 words, 40-bits/word maximum, 4 Sequential

Queues total

IDT72T55258 - 16,384 words, 40-bits/word maximum, 4 Sequential

Queues total

IDT72T55268 - 32,768 words, 40-bits/word maximum, 4 Sequential

Queues total

User Selectable Mux / Demux / Broadcast Write Modes

Mux Mode offers 4:1 architecture

- Five discrete clock domains, four write clocks and one read clock

- Four separate write ports, writes data to four independent Queues

- One single read port, capable of reading from any four Queues

- Selectable single or double data rate (SDR/DDR) on read and write

- 10-bit wide write ports in single data rate, doubles internally in double

- 40-bit wide read port, doubles internally in double data rate,

- Bus Matching on the Read Port x10/x20/x40 (SDR/DDR)

- Fully independent status flags for every Queue

- Composite Empty/Output Ready Flag monitors currently selected

- Dedicated partial reset for every Queue

ports

data rate

selectable between the four independent Queues

Queue

Queue 3

Data In

Queue 1

Data In

Queue 2

Data In

Queue 0

Data In

D[19:10]

D[29:20]

D[39:30]

FF2/ IR2

D[9:0]

WCLK2

FF0/IR0

FF1/IR1

FF3/IR3

WCLK0

WCLK1

WCLK3

WEN0

WCS0

WEN1

WCS1

WEN2

WCS2

WEN3

WCS3

PAF0

PAF1

PAF2

PAF3

2.5V QUADMUX DDR FLOW-CONTROL DEVICE

WITH MUX/DEMUX/BROADCAST FUNCTIONS

8,192 x 40 x 4

16,384 x 40 x 4

32,768 x 40 x 4

Mux Mode

32,768 x 40

16,384 x40

32,768 x 40

16,384 x40

8,192 x 40

Queue 2

Queue 3

Queue 0

Queue 1

• • • • •

Demux Mode offers 1:4 architecture

- Five discrete clock domains, one write clock and four read clocks

- Four separate read ports, read data from four independent Queues

- One single write port, capable of writing to any four Queues

- Selectable single or double data rate on read and write ports

- 10-bit wide read ports in single data rate, doubles internally in double

- 40-bit wide write port, doubles internally in double data rate,

- Bus Matching on the Write Port x10/x20/x40 (SDR/DDR)

- Fully independent status flags for every Queue

- Composite Full/Input Ready Flag monitors currently selected Queue

- Dedicated partial reset for every Queue

Broadcast Write Mode offers, 1:4 architecture (with simultaneous

writes to all Queues)

- Five discrete clock domains, one write clock and four read clocks

- Four separate read ports, read data from four independent Queues

- One single write port, writes to all four independent Queues

- 10-bit wide read ports in single data rate, doubles internally in double

- 40-bit wide write port, doubles internally in double data rate

- Selectable single or double data rate on read and write ports

- Bus-Matching on the write port x10/x20/x40 (SDR/DDR)

data rate

selectable between the four independent Queues

simultaneously

data rate

(See next pages for Demux and Broadcast modes)

6157 drw01

x10,x20,x40

Q[39:0]

CEF/COR

EF0/OR0

PAE0

EF1/OR1

PAE1

EF2/OR2

PAE2

EF3/OR3

PAE3

RCLK0

REN0

RCS0

OE0

OS[1:0]

FEBRUARY 2009

Data Out

IDT72T55248

IDT72T55258

IDT72T55268

DSC-6157/5

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IDT72T55268L5BB Summary of contents

Page 1

FEATURES • • • • • Choose from among the following memory organizations: IDT72T55248 - 8,192 words, 40-bits/word maximum, 4 Sequential Queues total IDT72T55258 - 16,384 words, 40-bits/word maximum, 4 Sequential Queues total IDT72T55268 - 32,768 words, 40-bits/word maximum, 4 ...

Page 2

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K Features ...................................................................................................................................................................................................................... 1,4 Description ...................................................................................................................................................................................................................... 6 Pin Configuration ............................................................................................................................................................................................................. 8 Pin Descriptions .......................................................................................................................................................................................................... 9-13 Device ...

Page 3

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K Figure 1. QuadMux Block Diagram .................................................................................................................................................................................. 7 Figure 2a. AC Test Load ................................................................................................................................................................................................ 18 Figure ...

Page 4

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K FEATURES (CONTINUED) - Fully independent status flags for every Queue - Composite Full/Input Ready Flag ...

Page 5

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K FUNCTIONAL BLOCK DIAGRAMS (CONTINUED) Broadcast Mode WCLK0 WEN0 WCS0 D[39:0] Data In x10,x20,x40 FF0/ IR0 ...

Page 6

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with Mux/Demux/Broadcast functions 16K and 32K DESCRIPTION The IDT72T55248/72T55258/72T55268 QuadMux flow-control devices are ideal for many applications where data stream convergence ...

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