IDT72T55268L5BB IDT, Integrated Device Technology Inc, IDT72T55268L5BB Datasheet - Page 62

• Manufacturer Part Number: IDT72T55268L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L5BB

WCLK
NOTES:
1. m0 = PAF0 offset .
2. D = maximum Queue depth. For density of Queue with bus-matching, refer to the bus-matching section on page 19.
3. t
4. PAF0 is asserted and updated on the rising edge of WCLK0 only.
5. Select this mode by setting PFM HIGH during Master Reset.
6. RCS0 = LOW, WCS0 = LOW, WDDR = LOW, and RDDR = LOW.
WCLK0
NOTES:
1. The timing diagram shown is for Queue0. Queues1-3 exhibit the same behavior.
2. n0 = PAE0 offset.
3. For IDT Standard mode
4. For FWFT mode.
5. t
6. PAE0 is asserted and updated on the rising edge of WCLK0 only.
7. Select this mode by setting PFM HIGH during Master Reset.
8. RCS0 = LOW, WCS0 = LOW, WDDR = LOW, and RDDR = LOW.
RCLK0
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
REN0
RCLK0
WEN0
PAF0
between the rising edge of RCLK0 and the rising edge of WCLK0 is less than t
WEN0
the rising edge of WCLK0 and the rising edge of RCLK0 is less than t
REN0
PAE0
SKEW2
SKEW2
is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that PAE0 will go HIGH (after one RCLK0 cycle plus t
is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that PAF0 will go HIGH (after one WCLK0 cycle plus t
D - (m0 +1) words in Queue
t
CLKH
t
CLKL
(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out
(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out
t
ENS
t
t
CLKL
ENS
t
CLKL
t
PAFS
(1)
n0 + 1 words in Queue
n0 + 2 words in Queue
Figure 36. Synchronous Programmable Almost-Empty Flag Timing
t
Figure 35. Synchronous Programmable Almost-Full Flag Timing
ENH
t
SKEW2
1
t
ENH
(4)
t
PAES
(2)
(3)
1
,
2
SKEW2
, then the PAE0 deassertion may be delayed one extra RCLK0 cycle.
SKEW2
2
62
, then the PAF0 deassertion time may be delayed one extra WCLK0 cycle.
t
ENS
t
ENS
D - m0 words in Queue
t
t
ENH
SKEW2
t
ENH
(3)
1
1
n0 words in Queue
COMMERCIAL AND INDUSTRIAL
(1)
TEMPERATURE RANGES
2
FEBRUARY 01, 2009
PAES
t
2
PAFS
). If the time between
PAFS
). If the time
6157 drw32
6157 drw33