IDT72T55268L6-7BBI IDT, Integrated Device Technology Inc, IDT72T55268L6-7BBI Datasheet - Page 12

• Manufacturer Part Number: IDT72T55268L6-7BBI
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L6-7BBI

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.7ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L6-7BBI

PIN DESCRIPTIONS (CONTINUED)
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
TCK
(C13)
TDI
(B13)
TDO
(B17)
TMS
(C14)
TRST
(C15)
WCLK0
(F1)
WCLK1-(G1)
WCLK2-(H1)
WCLK3-(J1)
WCS0
(U1)
WCS1-(U2)
WCS2-(U3)
WCS3-(T1)
WDDR
(C7)
WEN0
(T2)
WEN1-(T3)
WEN2-(R1)
WEN3-(R2)
Symbol &
Pin No.
(3)
(3)
(3)
(3)
(3)
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
JTAG Mode Select
JTAG Reset
Write Clock 0
Write Chip Select 0
Write Chip Select
1, 2, 3
Write Port DDR
Write Enable 0
Write Enable 1/2/3
Write Clock 1/2/3
Name
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller is automatically
HSTL-LVTTL If Mux mode is selected this is the clock input for Queue 0. All write port operations to Queue 0 will
HSTL-LVTTL If Mux mode is selected these are the clock inputs for Queues 1, 2, and 3 respectively. All write
HSTL-LVTTL If Mux mode is selected this is the write chip select input for Queue 0. All write operations on Queue 0
HSTL-LVTTL If Mux mode is selected these are the write chip select inputs for Queues 1, 2 and 3 respectively. All
HSTL-LVTTL If Mux mode is selected this is the write enable input for Queue 0. All write operations on Queue 0 will
I/O TYPE
OUTPUT
CMOS
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
LVTTL
(1)
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the
rising edge of TCK and output TDO change on the falling edge of TCK. If the JTAG function is not used
this signal needs to be tied to GND.
operation, test data is serially loaded via the TDI on the rising edge of TCK to either the Instruction
Register, ID Register, Bypass Register or Boundary Scan chain. An internal pull-up resistor forces
TDI HIGH if left unconnected.
operation, test data is scanned to the TDO output on the falling edge of TCK from either the Instruction
Register, ID Register, Bypass Register and Boundary Scan chain. This output is high impedance
except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
the device through its TAP controller states sampled on the rising edge of TCK. An internal pull-up
resistor forces TMS HIGH if left unconnected.
reset upon power-up. If the TAP controller is not properly reset then the Queue outputs will always
be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST
can be tied with MRS to ensure proper Queue operation. If the JTAG function is not used then this
signal needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected.
be synchronous to this clock input.
If Demux or Broadcast mode is selected this is the clock input for the write port. All write port operations
will be synchronous to this clock input. Sampled on the rising edge of WCLK and independent of WDDR.
port operations on Queue1, Queue 2 and Queue 3 will be synchronous to clock inputs WCLK1,
WCLK2 and WCLK3 respectively.
If Demux or Broadcast mode is selected these clock inputs are ignored and can be tied to GND.
will occur synchronous to the WCLK0 input provided that WEN0 and WCS0 are LOW.
If Demux or Broadcast mode is selected this is the write chip select input for the write port. All write
operations will occur synchronous to the WCLK0 input provided that WEN0 and WCS0 are LOW.
Sampled on the rising edge of WCLK and independent of WDDR.
write operations on Queue 1, Queue 2 and Queue 3 will occur synchronous to the WCLK1, 2 and 3
respectively, provided that the corresponding write enable and write chip select inputs are LOW.
Sampled on the rising edge of WCLK and independent of WDDR.
If Demux or Broadcast mode is selected these inputs are ignored and can be tied HIGH.
During master reset, this pin selects the input port to operate in DDR or SDR format. If WDDR is HIGH,
then a word is written on the rising and falling edge of the appropriate WCLK0, 1, 2 and 3 input.
If WDDR is LOW, then a word is written only on the rising edge of the appropriate WCLK1, 1, 2 and
3 inputs.
occur synchronous to the WCLK0 input provided that WEN0 and WCS0 are LOW.
If Demux or Broadcast mode is selected this is the write enable input for the write port. All write
operations will occur synchronous to the WCLK0 clock input provided that WEN0 and WCS0 are LOW.
If Mux mode is selected these are the write enable inputs for Queues 1, 2 and 3 respectively. All write
operations on Queue 1, Queue 2 and Queue 3 will occur synchronous to the WCLK1, 2 and 3 inputs
respectively, provided that the corresponding write enable and write chip select inputs are LOW.
If Demux or Broadcast mode is selected these inputs are ignored and can be tied HIGH.
12
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 01, 2009