IDT72T55268L6-7BBI IDT, Integrated Device Technology Inc, IDT72T55268L6-7BBI Datasheet - Page 37

• Manufacturer Part Number: IDT72T55268L6-7BBI
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55268L6-7BBI

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.7ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 150mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55268L6-7BBI

JTAG TIMING SPECIFICATIONS
(IEEE 1149.1 COMPLIANT)
Test Access Port (IEEE 1149.1) specifications. Five additional pins (TDI, TDO,
TMS, TCK and TRST) are provided to support the JTAG boundary scan
interface. Note that IDT provides appropriate Boundary Scan Description
Language program files for these devices.
TEST ACCESS PORT (TAP)
internal JTAG state machine. It consists of four input ports (TCLK, TMS, TDI,
TRST) and one output port (TDO).
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
The JTAG test port in this device is fully compliant with the IEEE Standard
The TAP interface is a general-purpose port that provides access to the
All inputs
Eg: Dins, Clks
(BSDL file
describes the
chain order)
TDI
TMS
TCK
TRST
TAP
In Pad
In Pad
Incell
Incell
Flag Offset Chain
Figure 8. JTAG Architecture
Instruction
Register
Bypass
Instruction
Select
Enable
Core
Logic
ID
37
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and updating of data passed through the TDI
serial input.
The Standard JTAG interface consists of seven basic elements:
•
•
•
•
•
•
•
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture
The TAP controller is a synchronous finite state machine that responds to
Outcell
Outcell
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Bypass Register (BYR)
ID Code Register
Flag Programming
Out Pad
Out Pad
COMMERCIAL AND INDUSTRIAL
All outputs
TEMPERATURE RANGES
FEBRUARY 01, 2009
6157 drw14
TDO