IDT89TTM552BL IDT, Integrated Device Technology Inc, IDT89TTM552BL Datasheet - Page 16

• Manufacturer Part Number: IDT89TTM552BL
• Description: IC TRAFFIC MANAGER 1192-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89TTM552BL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89TTM552BL

89TSF500 Power, Reset, and Initialization Sequencing Requirements
Power Supply Power-Up Sequence
ramp up before all other power supply pins:
short-circuit current or bus contention during the power-up period. Such events can occur because of an unknown state of output enable of the bidirec-
tional buffers. After core power ramps up (with RESET_N asserted), the bidirectional I/O lines enter normal operating mode.
Power Supply Power-Down Sequence
high transient current from short-circuit current or bus contention can also occur during the power-down period. We recommend appropriate
sequencing. All 3.3V I/O power should ramp down before the 1.8V core (VDD) power:
after the 1.8V core power supply (within about 50 ms), the system designer can safely ignore this recommendation.
PLL Power-Up Initialization
sequence. Figure 12 shows the initialization sequence.
IDT 89TSF500
There is a power supply power-up sequence requirement that addresses potential latchup issues with some I/O buffers. All 3.3V I/O power must
Further, IDT recommends that the designer use current limiting resistors on the bidirectional ZBus pins to limit potential high transient current from
Because the power supply power-off state clears any latchup condition, the power-down sequence is not dictated by latchup. However, potential
However, if appropriate current limiting techniques (e.g., series resistors) are employed and the 2.5V and 1.5V power supplies ramp down soon
PLL inputs into the 89TSF500, from an external device such as the ZBus bridge in IDT’s reference system, require a special initialization
PLL initialization is necessary only at power-up. If the PLLs fail to lock, repeatedly assert PLL_RST until they do.
– 3.3V I/O (VDD_IO, VDDP33, VDD_REFCLKn)
– All other power supply pins
– 3.3V I/O (VDD_IO)
– 1.8V core (VDD)
Note: The 89TSF500 must be reset after PLL initialization. Hold RESET_N low for at least 16 clocks (SYS_CLK) after PLL initialization
completes.
Power Supplies
PLL_DIV_RST_N
PLL_CORE_LCK
PLL_SYS_LCK
RESET_N
PLL_RST
Clock
*Notice: The information in this document is subject to change without notice
Figure 12 PLL Power-Up Initialization for the 89TSF500
clock present and stable
1 µs min
16 of 37
10 ns min
T
ACQUIRE
, 15 µs min
T
Repeat if necessary until
lock is achieved.
RESET
, 16 clocks min
···
November 23, 2004