IDT89TTM552BL IDT, Integrated Device Technology Inc, IDT89TTM552BL Datasheet - Page 9

• Manufacturer Part Number: IDT89TTM552BL
• Description: IC TRAFFIC MANAGER 1192-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89TTM552BL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89TTM552BL

89TSF500 AC Characteristics
IDT 89TSF500
Unless otherwise stated, the following parameters are provided given the conditions outlined in Table 8.
Symbol
Symbol
Symbol
T
T
T
T
T
T
T
T
T
KQHZZB
RSYSCI
KQLZZB
T
D
FSYSCI
T
T
KQVZB
KQXZB
T
f
D
RZBCI
FZBCI
JSYS
SYS
f
RZBI
FZBI
SZB
HZB
SYS
ZB
ZB
System clock frequency (125 MHz ±0.1MHz)
Jitter requirements (peak to peak) for system clock. Peak to peak jitter require-
ments apply to entire range of allowed system clock frequencies.
Percentage duty cycle for system clock
System clock input rise time (10% to 90%)
System clock input fall time (90% to 10%)
ZBus clock frequency
Percentage duty cycle for ZBus clock
ZBus clock input rise time (10% to 90%)
ZBus clock input fall time (90% to 10%)
ZBus clock rising edge to output valid
ZBus clock rising edge to output invalid
ZBus clock rising edge to output low Z
ZBus clock rising edge to output high Z
Input setup time from ZBus clock rising edge
Input hold time from ZBus clock rising edge
Input rise time (10% to 90%)
Input fall time (90% to 10%)
*Notice: The information in this document is subject to change without notice
Table 12 89TSF500 ZBus Interface Timing
Parameter
Table 10 89TSF500 System Clock Timing
Parameter
Parameter
Table 11 89TSF500 ZBus Clock Timing
9 of 37
124.9
Min
Min
Min
1.0
1.0
1.0
5.0
1.0
—
45
—
—
30
45
—
—
—
—
—
Typical
Typical
Typical
f
SYS
125
50
50
—
—
—
—
—
—
—
—
—
—
—
—
—
/ 4
Max
Max
Max
125.1
TBD
TBD
TBD
TBD
TBD
TBD
33.1
10.0
10.0
10.0
100
55
55
November 23, 2004
Units
Units
Units
MHz
MHz
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%