NBSG16BAHTBG ON Semiconductor, NBSG16BAHTBG Datasheet - Page 8

• Manufacturer Part Number: NBSG16BAHTBG
• Description: IC RCVR/DVR RSECL SIGE 16FCBGA
• Manufacturer: ON Semiconductor
• Type: Transceiverr

Specifications of NBSG16BAHTBG

• Applications: Instrumentation
• Mounting Type: Surface Mount
• Package / Case: 16-FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
17. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to V
18. See Figure 6. t
19. V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
20. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to V
21. See Figure 6. t
22. V
Table 8. AC CHARACTERISTICS for FCLGA−16
V
Table 9. AC CHARACTERISTICS for QFN−16
V
Symbol
Symbol
f
t
t
t
t
V
t
t
f
t
t
t
t
V
t
t
max
PLH
PHL
SKEW
JITTER
r
f
max
PLH
PHL
SKEW
JITTER
r
f
CC
CC
INPP
INPP
INPP(max)
INPP(max)
,
,
= 0 V; V
= 0 V; V
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Maximum Frequency
(See Figure 4. f
Propagation Delay to
Output Differential
Duty Cycle Skew (Note 18)
RMS Random Clock Jitter
Peak−to−Peak Data Dependent Jitter
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 19)
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
Maximum Frequency
(See Figure 4. f
Propagation Delay to
Output Differential
Duty Cycle Skew (Note 21)
RMS Random Clock Jitter
Peak−to−Peak Data Dependent Jitter
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 22)
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
EE
EE
cannot exceed V
cannot exceed V
= −3.465 V to −2.375 V or V
= −3.465 V to −2.375 V or V
skew
skew
= |t
= |t
Characteristic
PLH
Characteristic
PLH
max
max
− t
− t
/JITTER) (Note 17)
/JITTER) (Note 20)
CC
CC
PHL
PHL
− V
− V
| for a nominal 50% differential clock input waveform.
| for a nominal 50% differential clock input waveform.
EE
EE
f
f
f
f
in
in
in
in
CC
CC
< 10 Gb/s
< 10 Gb/s
< 10 GHz
< 10 GHz
= 2.375 V to 3.465 V; V
= 2.375 V to 3.465 V; V
Q, Q
Q, Q
http://onsemi.com
10.7
10.7
Min
Min
90
75
30
90
75
20
−40°C
−40°C
TBD
TBD
Typ
Typ
110
110
0.2
0.2
12
45
12
30
8
3
3
EE
EE
= 0 V
= 0 V
2600
2600
Max
Max
130
130
15
75
15
50
1
2
10.7
10.7
Min
Min
100
100
75
20
75
20
25°C
25°C
CC
CC
TBD
TBD
Typ
120
Typ
120
0.2
0.2
12
40
12
30
3
3
− 2.0 V. Input edge rates 40 ps (20% − 80%).
− 2.0 V. Input edge rates 40 ps (20% − 80%).
2600
2600
Max
Max
140
140
15
65
15
50
1
2
10.7
10.7
Min
105
Min
75
20
95
75
20
85°C
85°C
TBD
TBD
Typ
125
Typ
125
0.2
0.2
12
40
12
30
3
3
2600
2600
Max
Max
145
145
15
65
15
50
1
2
Unit
GHz
Unit
GHz
mV
mV
ps
ps
ps
ps
ps
ps
ps
ps