STV0974E/TR STMicroelectronics, STV0974E/TR Datasheet - Page 52

• Manufacturer Part Number: STV0974E/TR
• Description: IC DSP IMAGING VGA CMOS 6X6TFBGA
• Manufacturer: STMicroelectronics

Specifications of STV0974E/TR

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 56-TFBGA
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• For Use With: 497-3891 - KIT DEMO W/VS6552
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3887-2; STV0974E/TR

STV0974
4.9.3.4 Firmware patching
4.10
The STV0974 has some firmware patching capabilities addressable through I
microprocessor interfaces through control registers firmware patch code downloads. Up to 15
different patches can be downloaded within a limit of 512 bytes of RAM.
The patch space starts from address 0x8600.
Patch structure:
“disable all patches”
“set address to patch”
“set offset of patch in memory”
“write patch in memory (starting from address 0x8600 + patch memory offset)”
“enable all patches”
The state in which to download the patch depends on the nature of the patch, most likely either idle
or sleep mode. Please contact ST support for patch delivery and recommendations for ideal use.
Additional features
There are a number of additional features which are supported by the STV0974, however
implementation of these features is not supported by this datasheet. Please contact the ST support
team for support of these features if you have a specific requirement.
Patch enable
Patch address
Patch memory
offset
●
●
●
The polarity of the HSYNC and VSYNC signal can be programmed. However, these are non-
standard settings.
The transmitted byte order of the RGB and YUV is programmable.
The viewfinder color matrix can be programmed to match the characteristics of a local LCD
display.
Name
0x84BF
Ox8481
0x84A0
0x84A1
0x8480
Index
R/W
W
W
W
Table 36 : Patch control registers
RRRR.RRDD
RRRR.RRRR
RRRR.RRRR
1DDD.DDDD
DDDD.DDDD
Format
default
bit [1:0] = 01 patch enabled
bit [7:2] = 10 patch disabled
bit [15:0] = Reserved
Patch address delivered by ST
bit [15] = 1
bit [14:0] = Patch memory offset
Description
Functional description
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