KS8995XA Micrel Inc, KS8995XA Datasheet - Page 40

• Manufacturer Part Number: KS8995XA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995XA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1604 - EVAL KIT EXPERIMENTAL KS8995XA
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

KS8995XA
MIIM Registers
The “PHYAD” defined by IEEE is assigned as “0x1” for port 1, “0x2” for port 2, “0x3” for port 3, “0x4” for port 4, “0x5” for port
5. The “REGAD” supported are 0,1,2,3,4,5.
M9999-051305
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.
Address
Register 0: MII Control
15
14
13
12
11
10
Address
Register 97 (0x61): TOS Priority Control Register 1
7-0
Register 98 (0x62): TOS Priority Control Register 2
7-0
Register 99 (0x63): TOS Priority Control Register 3
7-0
Register 100 (0x64): TOS Priority Control Register 4
7-0
Register 101 (0x65): TOS Priority Control Register 5
7-0
Register 102 (0x66): TOS Priority Control Register 6
7-0
Register 103 (0x67): TOS Priority Control Register 7
7-0
Register 104 (0x68): MAC Address Register 0
7-0
Register 105 (0x69): MAC Address Register 1
7-0
Register 106 (0x6A): MAC Address Register 2
7-0
Register 107 (0x6B): MAC Address Register 3
7-0
Register 108 (0x6C): MAC Address Register 4
7-0
Register 109 (0X6D): MAC Address Register 5
7-0
Name
Soft reset
Loop back
Force 100
AN enable
Power down
Isolate
Name
DSCP[55:48]
DSCP[47:40]
DSCP[39:32]
DSCP[31:24]
DSCP[23:16]
DSCP[15:8]
DSCP[7:0]
MACA[47:40]
MACA[39:32]
MACA[31:24]
MACA[23:16]
MACA[15:8]
MACA[7:0]
Description
Description
1 = PHY soft reset.
0 = normal operation.
1 = loop back mode (loop back at PHY).
0 = normal operation.
1 = 100Mbps.
0 = 10Mbps.
1 = auto-negotiation enabled.
0 = auto-negotiation disabled.
1 = power down.
0 = normal operation.
Not supported.
40
Mode
RO
R/W
R/W
R/W
R/W
RO
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
1
0
0
Default
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0x00
0x10
0xA1
0xff
0xff
0xff
Micrel, Inc.
May 2005