KS8993MI Micrel Inc, KS8993MI Datasheet - Page 73

• Manufacturer Part Number: KS8993MI
• Description: IC SWITCH 10/100 3PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8993MI

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Supply Voltage (min): 1.71/3.135V
• Power Dissipation: 800mW
• Supply Current: 0.1/0.19A
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 576-1013 - BOARD EVAL EXPERIMENT KS8993M
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 576-1014

Additional Information
Both “Per Port” and “All Port Dropped Packet” MIB counters do not indicate overflow. The application must keep
track of overflow conditions for these counters.
“All Port Dropped Packet” MIB counters do not indicate if count is valid. The application must keep track of valid
conditions for these counters.
To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are
160 registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2
minutes. It is recommended that the software read all the counters at least every 30 seconds.
A high performance SPI master is also recommended to prevent counters overflow.
Per Port MIB counters are designed as “read clear.” That is, these counters will be cleared after they are read.
“All Port Dropped Packet” MIB counters are not cleared after they are read.
Micrel, Inc.
October 2008
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Then,
Then
Read reg. 117 (counter value 30-24) // If bit 30 = 0, restart (reread) from this register
Read reg. 118 (counter value 23-16)
Read reg. 119 (counter value 15-8)
Read reg. 120 (counter value 7-0)
Write to reg. 110 with 0x1d (read MIB counter selected)
Write to reg. 111 with 0x00 (trigger the read operation)
Read reg. 119 (counter value 15-8)
Read reg. 120 (counter value 7-0)
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M9999-020606
KSZ8993M/ML