MC33780EGR2 Freescale Semiconductor, MC33780EGR2 Datasheet - Page 18

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MC33780EGR2

Manufacturer Part Number
MC33780EGR2
Description
IC DBUS MASTER DUAL DIFF 16-SOIC
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC33780EGR2

Applications
*
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
automatically to a slow acquisition mode (180.224 ms per
update cycle, based on 4.0 MHz clock).
SPREADER LOGIC
sequence (PRBS) generator and time compensation
circuitry. The PRBS can generate maximal length sequences
of 6, 7, 11, and 15 bits. Maximal length means there is no
repeat of the sequence until 2
where n is the selected length.
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FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The Spreader Logic contains a pseudo-random binary
n
counts have been reached,
periods are chosen in a way to keep the length of the frame
constant, provided that the total number of bits is even. This
is useful if the time between samples made by the slaves
must be kept relatively constant. Without this feature, the time
from sample-to-sample would vary randomly.
control whether the deviation is enabled or disabled.
value of the digital word to the Spreader DAC at the
beginning of a DBUS bit. When spreading is enabled, these
changes will occur once per DBUS bit-time.
A special feature of the Spreader Logic is that the bit
The DEV1 and DEV0 bits in the DnSSCTRL register
The Spreader Logic is synchronized to only change the
Analog Integrated Circuit Device Data
Freescale Semiconductor

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