NBSG16MMN ON Semiconductor, NBSG16MMN Datasheet - Page 8

• Manufacturer Part Number: NBSG16MMN
• Description: IC RCVR/DRVR CML 2.5V/3.3V 16QFN
• Manufacturer: ON Semiconductor
• Type: Transceiverr

Specifications of NBSG16MMN

• Applications: Instrumentation
• Mounting Type: Surface Mount
• Package / Case: 16-TFQFN Exposed Pad
• Logic Family: NBSG
• Logic Type: Receiver and Driver Translator Buffer
• Supply Voltage (max): - 3.465 V, 3.465 V
• Supply Voltage (min): - 2.375 V, 2.375 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Rate: 10000 Mbps
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): / /
• Supply Current: 51 mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: NBSG16MMNOS

Table 8. AC CHARACTERISTICS
Symbol
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
15. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to V
16. See Figure 8 t
17. V
18. Additive RMS jitter with 50% duty cycle clock signal at 10GHz.
19. Additive Peak−to−Peak data dependent jitter with NRZ PRBS2
V
t
t
t
t
V
t
t
PLH
PHL
SKEW
JITTER
r
f
OUTPP
INPP
operating in differential mode.
,
INPP(max)
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
Output Voltage Amplitude
(See Figure 4) (Note 15)
Propagation Delay to
Output Differential
Duty Cycle Skew (Note 16)
RMS Random Clock Jitter (Note 18)
Peak−to−Peak Data Dependent Jitter (Note 19)
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 17)
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
cannot exceed V
skew
= |t
PLH
Characteristic
− t
CC
500
450
400
350
300
250
200
150
100
Input Clock Frequency (f
50
PHL
0
− V
0
| for a nominal 50% differential clock input waveform.
Figure 4. Output Voltage Amplitude (V
EE
V
V
CC
. (Applicable only when V
V
CC
CC
− V
1
− V
= 0 V; V
EE
EE
= 3.3 V
2
= 2.5 V
f
f
f
in
in
in
EE
f
in
< 10 Gb/s
< 10 GHz
< 10 GHz
< 7 GHz
= −3.465 V to −2.375 V or V
3
http://onsemi.com
Q, Q
FREQUENCY (GHz)
in
) at Ambient Temperature (Typical)
4
CC
Min
31
300
200
90
75
21
− V
8
−1 data rate at 10 Gb/s.
EE
5
−40°C
Typ
400
250
110
< 2500 mV). Input voltage swing is a single−ended measurement
0.2
35
3
8
6
2500
Max
150
15
15
53
1
OUTPP
CC
7
Min
= 2.375 V to 3.465 V; V
300
200
100
75
21
) versus
8
CC
25°C
Typ
400
250
120
0.2
35
3
8
. Input edge rates 40 ps (20% − 80%).
9
2500
Max
150
15
15
53
1
10
Min
300
100
100
75
21
EE
= 0 V
Typ
400
150
125
85°C
0.2
35
3
8
2500
Max
155
1.0
15
15
53
Unit
mV
mV
ps
ps
ps
ps