SI8440BB-D-IS Silicon Laboratories Inc, SI8440BB-D-IS Datasheet - Page 21
![IC ISOLATOR 4CH 5.5V 16-SOIC](/photos/7/41/74106/16-soic__7_5mmwidth__sml.jpg)
SI8440BB-D-IS
Manufacturer Part Number
SI8440BB-D-IS
Description
IC ISOLATOR 4CH 5.5V 16-SOIC
Manufacturer
Silicon Laboratories Inc
Series
ISOpror
Datasheet
1.SI8442AB-D-IS.pdf
(38 pages)
Specifications of SI8440BB-D-IS
Number Of Channels
4
Package / Case
16-SOIC (0.300", 7.5mm Width)
Inputs - Side 1/side 2
4/0
Isolation Rating
2500Vrms
Voltage - Supply
2.7 V ~ 5.5 V
Data Rate
150Mbps
Propagation Delay
6ns
Output Type
Tri-State
Operating Temperature
-40°C ~ 125°C
Mounting Style
SMD/SMT
Propagation Delay Time
6 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Supply Current
6 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1760-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI8440BB-D-IS
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
SI8440BB-D-ISR
Manufacturer:
ST
Quantity:
101
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
Si8440
Si8441
Si8442
Si8445
P/N
operation is summarized for each isolator product in Table 13. These inputs are internally pulled-up to local VDD by a
3 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize
noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is
recommended they be connected to an external logic level, especially if the Si84xx is operating in a noisy environment.
(EN = 0) in Revision C. Revision D outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 25 for more details.
EN1
—
—
—
H
X
X
H
X
X
L
L
1,2
EN2
—
H
X
X
H
X
X
H
L
L
L
1,2
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Outputs B1, B2, B3, B4 are disabled and Logic Low or in high impedance state.
Output A4 enabled and follows the input state.
Output A4 disabled and Logic Low or in high impedance state.
Outputs B1, B2, B3 are enabled and follow the input state.
Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state.
Outputs A3 and A4 are enabled and follow the input state.
Outputs A3 and A4 are disabled and Logic Low or in high impedance state.
Outputs B1 and B2 are enabled and follow the input state.
Outputs B1 and B2 are disabled and Logic Low or in high impedance state.
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Table 13. Enable Input Truth Table
Rev. 1.3
Operation
1
Si8440/41/42/45
3
3
3
3
21
3