HCPL-M601 Avago Technologies US Inc., HCPL-M601 Datasheet - Page 7

• Manufacturer Part Number: HCPL-M601
• Description: OPTOCOUPLER 10MBD LOGIC SO-5
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-M601

• Package / Case: 5-SOP
• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 50mA
• Data Rate: 10MBd
• Propagation Delay High - Low @ If: 25ns @ 7.5mA
• Current - Dc Forward (if): 20mA
• Input Type: DC
• Output Type: Open Collector
• Mounting Type: Surface Mount
• Isolation Voltage: 3750 Vrms
• Maximum Continuous Output Current: 50 mA
• Maximum Fall Time: 10 ns
• Maximum Forward Diode Current: 20 mA
• Maximum Rise Time: 24 ns
• Minimum Forward Diode Voltage: 1.4 V
• Output Device: Logic Gate Photo IC
• Configuration: 1 Channel
• Maximum Baud Rate: 10 MBps
• Maximum Forward Diode Voltage: 1.75 V
• Maximum Reverse Diode Voltage: 5 V
• Maximum Power Dissipation: 85 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Specifications
Over recommended temperature (T
*All typicals at T
Notes:
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. t
7
Mode Transient
Immunity at High
Output Level
Mode Transient
Immunity at Low
Output Level
Propagation
Delay Time
to High
Output Level
Propagation
Delay Time
to Low
Output Level
Propagation
Delay Skew
Pulse Width
Distortion
Output Rise
Time
(10%-90%)
Output Fall
Time
(10%-90%)
Common
Common
Parameter
1. Bypassing of the power supply line is required with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler. The total lead length be-
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
5. The t
6. The t
7. CM
8. CM
9. For sinusoidal voltages, (|dV
tween both ends of the capacitor and the isolator pins should not exceed 10 mm.
20 mA.
tion current limit, I
output pulse.
output pulse.
2.0 V).
V).
operating condition range.
PSK
H
L
is equal to the worst case differ ence in t
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V
PLH
PHL
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V
propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the
propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the
A
= 25°C, V
I-O
|t
Symbol
PHL
≤ 5 μA).
|CM
|CM
t
t
t
t
t
PLH
PHL
PSK
rise
fall
- t
H
H
CC
PLH
|
|
CM
= 5 V.
|/dt)
|
max
Device
M600
M601
M611
M600
M601
M611
HCPL-
= Sf
A
CM
PHL
= -40°C to 85°C), V
V
CM(p-p)
and/or t
10,000
10,000
Min.
5,000
5,000
20
25
.
PLH
10,000
10,000
15,000
10,000
10,000
15,000
that will be seen between units at any given temperature within the worst case
Typ.*
3.5
48
50
24
10
CC
Max.
= 5 V, I
100
100
75
75
40
35
F
V/μs
Unit
= 7.5 mA unless otherwise specified.
ns
T
T
V
V
V
V
V
V
A
A
CM
CM
CM
CM
CM
CM
= 25°C
= 25°C
= 10 V
= 50 V
= 1000 V
= 10 V
= 50 V
= 1000 V
Test Conditions
R
I
T
R
I
T
F
R
C
V
V
F
A
A
L
L
L
= 0 mA
= 7.5 mA
L
O(min)
O(max)
= 25°C
= 350 Ω
= 350 Ω
= 25°C
= 350 Ω
= 15 pF
RMS
for 1 second (Leakage detec-
= 2 V
= 0.8 V
Fig.
6, 7
6, 7
10
10
11
11
8
8
9
OUT
5
Note
7, 9
8, 9
OUT
10,
11
10
6
> 0.8
>