DS1982-F3+ Maxim Integrated Products, DS1982-F3+ Datasheet - Page 12

• Manufacturer Part Number: DS1982-F3+
• Description: IBUTTON 1KBit ADD-ONLY F3
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1982-F3+

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 128B
• Memory Type: EPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS1982
initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will
send eight additional read time slots and receive an 8-bit CRC that is the result of shifting into the CRC
generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the
8-bit CRC has been received, data is again read from the 1024-bit EPROM data field starting at the next
page. This sequence will continue until the final page and its accompanying CRC are read by the bus
master. Thus each page of data can be considered to be 33 bytes long, the 32 bytes of user-programmed
EPROM data and an 8-bit CRC that gets generated automatically at the end of each page.
This type of read differs from the Read Memory command that simply reads each page until the end of
address space is reached. The Read Memory command only generates an 8-bit CRC at the end of memory
space that often might be ignored, since in many applications the user would store a 16-bit CRC with the
data itself in each page of the 1024-bit EPROM data field at the time the page was programmed. The
Read Data/Generate 8-bit CRC command provides an alternate read capability for applications that are
“bit-oriented” rather than “page-oriented” where the 1024-bit EPROM information may change over time
within a page boundary, making it impossible to program the page once and include an accompanying
CRC that will always be valid. Therefore, the Read Data/Generate 8-Bit CRC command concludes each
page with the DS1982 generating and supplying an 8-bit CRC that is based on and therefore is always
consistent with the current data stored in each page of the 1024-bit EPROM data field. After the 8-bit
CRC of the last page is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is
issued. The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a
Reset Pulse.
WRITE MEMORY [0Fh]
The Write Memory command is used to program the 1024–bit EPROM data field. The bus master will
follow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of
data (D7:D0). An 8-bit CRC of the command byte, address bytes, and data byte is computed by the
DS1982 and read back by the bus master to confirm that the correct command word, starting address, and
data byte were received.
The highest starting address within the DS1982 is 007FH. If the bus master sends a starting address
higher than this, the nine most significant address bits are set to 0 by the internal circuitry of the chip.
This will result in a mismatch between the CRC calculated by the DS1982 and the CRC calculated by the
bus master, indicating an error condition.
If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-
Wire bus for 480 s) is issued by the bus master. Prior to programming, the entire unprogrammed
1024-bit EPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus
master that is set to a logical 0, the corresponding bit in the selected byte of the 1024–bit EPROM will be
programmed to a logical 0 after the programming pulse has been applied at that byte location.
After the 480 s programming pulse is applied and the data line returns to a 5-volt level, the bus master
issues eight read time slots to verify that the appropriate bits have been programmed. The DS1982
responds with the data from the selected EPROM address sent least significant bit first. This byte contains
the logical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in
bit positions where the byte issued by the master contains 0s, a Reset Pulse should be issued and the
current byte address should be programmed again. If the DS1982 EPROM data byte contains 0s in the
same bit positions as the data byte, the programming was successful and the DS1982 will automatically
increment its address counter to select the next byte in the 1024-bit EPROM data field. The least
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