SMC128CFB6E NUMONYX, SMC128CFB6E Datasheet - Page 14

• Manufacturer Part Number: SMC128CFB6E
• Description: COMPACT FLASH MEM CARD 128MB F3
• Manufacturer: NUMONYX

Specifications of SMC128CFB6E

• Memory Size: 128MB
• Memory Type: CompactFLASH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical interface
Table 8.
14/29
–IOWR
(PC card memory mode)
–IOWR
–IOWR
Ultra DMA Protocol Active)
–STOP
(True IDE mode - Ultra DMA
Protocol Active)
–OE
(PC card memory mode)
–OE
–ATASEL
(True IDE mode)
READY
(PC card memory mode)
–IREQ
(PC card I/O mode)
INTRQ
(True IDE mode)
–REG
(PC card memory mode)
–REG
(PC card I/O mode)
–DMACK
(True IDE mode)
(PC card I/O mode)
(True IDE mode - except
(PC card I/O mode)
Signal name
Signals description (continued)
Dir.
O
I
I
I
Pin
35
37
44
9
Not used.
The I/O write strobe pulse is used to clock I/O data on the
bus into the card controller registers. Clocking occurs on the
rising edge.
In True IDE mode, while Ultra DMA mode protocol is not
active, this signal has the same function as in PC Card I/O
mode.
When Ultra DMA mode protocol is supported, this signal
must be negated before entering Ultra DMA mode protocol.
In True IDE mode, while Ultra DMA mode protocol is active,
the assertion of this signal causes the termination of the
Ultra DMA burst.
This is an Output Enable strobe generated by the host
interface. It reads data and the CIS and configuration
registers.
Reads the CIS and configuration registers.
This input signal must be driven Low to enable true IDE
mode.
Indicates whether the card is busy (Low), or ready to accept
a new data transfer operation (High). The host socket must
provide a pull-up resistor. At power-up and reset, the Ready
signal is held Low until the commands are completed. No
access should be made during this time. The Ready signal
is held High whenever the card has been powered up with
Reset continuously disconnected or asserted.
Interrupt request. It is strobed Low to generate a pulse
mode interrupt or held Low for a level mode interrupt.
Active High interrupt request to the host.
Used to distinguish between common memory and register
(attribute) memory accesses. High for common memory,
Low for attribute memory.
Must be Low during I/O cycles when the I/O address is on
the bus.
The –DMACK input signal is used to acknowledge DMA
transfers. It is asserted by the host in response to DMARQ
to initiate the transfer.
When DMA mode is disabled,
-DMACK signal.
If the host does not support DMA mode, but only True IDE
mode, this signal should be driven High or tied to V
host.
Description
the card should ignore the
SMC01GCF, SMC08GCF
CC
by the