SMC01GCFC6E NUMONYX, SMC01GCFC6E Datasheet - Page 13

• Manufacturer Part Number: SMC01GCFC6E
• Description: COMPACT FLASH MEM CARD 1GB F3
• Manufacturer: NUMONYX

Specifications of SMC01GCFC6E

• Memory Size: 1GB
• Memory Type: CompactFLASH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMC01GCF, SMC08GCF
Table 8.
–IORD
(PC card memory mode)
–IORD
–IORD
Ultra DMA Protocol Active)
–HDMARDY
DMA Protocol DMA Read)
–HSTROBE
DMA Protocol DMA Write)
–CD1, –CD2
(PC card memory mode)
–CD1, –CD2
(PC card I/O mode)
–CD1, –CD2
(True IDE mode)
–CE1, –CE2
(PC card memory mode)
–CE1, –CE2
(PC card I/O mode)
–CS0, –CS1
(True IDE mode)
–CSEL
(PC card memory mode)
–CSEL
–CSEL
(PC card I/O mode)
(True IDE mode - except
(True IDE mode - in Ultra
(True IDE mode - in Ultra
(PC card I/O mode)
(True IDE mode)
Signal name
Signals description (continued)
Dir.
O
I
I
I
26,25
7,32
Pin
34
39
Not used.
I/O read strobe generated by the host. It gates I/O data onto
the bus.
In True IDE mode, while Ultra DMA mode is not active, this
signal has the same function as in PC Card I/O mode.
In True IDE mode when Ultra DMA mode DMA Read is
active, this signal is asserted by the host to indicate that the
host is read to receive Ultra DMA data-in bursts. The host
may negate -HDMARDY to pause an Ultra DMA transfer.
In True IDE mode when Ultra DMA mode DMA Write is
active, this signal is the data out strobe generated by the
host. Both the rising and falling edge of HSTROBE cause
data to be latched by the device. The host may stop
generating HSTROBE edges to pause an Ultra DMA data-
out burst.
These are connected to ground on the card. They are used
by the host to determine that the card is fully inserted into its
socket.
Same for all modes.
Same for all modes.
Used to select the card and to indicate whether a byte or a
word operation is being performed. –CE2 accesses the odd
Byte, –CE1 accesses the even byte or the odd byte
depending on A0 and –CE2. A multiplexing scheme based
on A0, –CE1, –CE2 allows 8-bit hosts to access all data on
D0 to D7.
Same as PC card memory mode.
–CS0 is the chip select for the task file registers, while –CS1
selects the alternate status register and the device control
register.
When –DMACK is asserted, -CS0 and –CS1 must be de-
asserted and data width is 16 bits.
Not used.
Not used.
This internally pulled up signal is used to configure the card
as a master or slave. When grounded it is configured as a
master, when open it is configured as a slave.
Description
Electrical interface
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