DS1961S-F3 Maxim Integrated Products, DS1961S-F3 Datasheet - Page 19

• Manufacturer Part Number: DS1961S-F3
• Description: IBUTTON EEPROM 1KBit SHA-1 2CAN
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1961S-F3

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 128B
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(TA1 and TA2), the DS1961S clears the EN_LFS flag. The lower five bits of the target address TA1 are
ignored because only the page number is relevant. If the target address as sent by the master is valid (i.e.,
in the range of 0000h and 007Fh), and the secret is not write-protected, the SHA engine starts. The master
must wait for t
master must wait for t
and t
AAh if the copy was successful, but does not modify the scratchpad if the SHA engine did not start
because of an incorrect address or because of write protection. The master should read at least one byte at
the conclusion of the copy delay. Reading AAh indicates that the copy was successful. Reading FFh
indicates that the copy was not successful because of an incorrect address or because of write protection.
Since the content of the scratchpad is used as a partial secret, the master must fill the scratchpad with a
known 8-byte data pattern using the write scratchpad command before it issues the compute next secret
command. Otherwise the new secret depends on data that was unintentionally left in the scratchpad from
previous commands.
Copy Scratchpad [55h]
The data memory of the DS1961S can be read without any restrictions. Executing the copy scratchpad
command to write new data to the memory or register page, however, requires the knowledge of the
device’s secret and the ability to perform an SHA-1 computation to generate the 160-bit MAC to start the
data transfer from the scratchpad to the memory. The master can perform the MAC computation in
software or use a DS1963S as a coprocessor. The coprocessor approach has the benefit that the secret
remains hidden in the coprocessor iButton. The sequence in which the resulting MAC needs to be sent to
the DS1961S is shown in Table 2. Tables 3A and 3B show how the various data components are entered
into the SHA engine. The SHA computation algorithm is explained later in this document.
Table 2. MESSAGE AUTHENTICATION CODE TRANSMISSION SEQUENCE
After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern,
which should have been obtained by an immediately preceding read scratchpad command. This 3-byte
pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that
order). If the authorization code matches and the target memory is not write-protected, the DS1961S
starts its SHA engine to compute a 160-bit MAC that is based on the current secret, all of the scratchpad
data, the first 28 bytes of the addressed memory page, and the first seven bytes of the identity register (the
byte at address 0097h is not used; see Table 3A). The duration of this computation is t
the voltage on the 1-Wire line must not drop below 2.8V. Simultaneously the master computes a MAC
from the same data and, after t
write to the EEPROM. Now the master waits for t
E[31:24]
D[31:24]
C[31:24]
B[31:24]
A[31:24]
PROG
The transmission is least significant bit first starting with register E.
the voltage on the 1-Wire bus must not fall below 2.8V. The DS1961S fills the scratchpad with
CSHA
during which the new secret is computed. Immediately following the SHA delay, the
PROG
E[23:16]
D[23:16]
C[23:16]
B[23:16]
A[23:16]
during which the new secret is copied to the secret register. During the t
CSHA
is expired, sends it to the DS1961S as evidence that it is authorized to
E[15:8]
D[15:8]
C[15:8]
B[15:8]
A[15:8]
19 of 36
PROG
during which the voltage on the 1-Wire bus must
E[7:0]
D[7:0]
C[7:0]
B[7:0]
A[7:0]
CSHA
Shift
Direction
, during which
CSHA