MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet - Page 14

• Manufacturer Part Number: MT4VDDT3232UY-6K1
• Description: MODULE DDR 128MB 167MHZ 172-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3232UY-6K1

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 333MT/s
• Package / Case: 172-UDIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 700mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13: I
DDR SDRAM components only
Notes: 1–5, 14, 49; notes appear on pages 17–20; 0°C
pdf: 09005aef808da768, source: 09005aef808d2e9a
DD4C16_32x32UG.fm - Rev. D 9/04 EN
OPERATING CURRENT: One device bank; Active-Precharge;
t
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4;
and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
changing once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle;
t
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle;
changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL =
4) with auto precharge,
and control inputs change only during Active READ or WRITE
commands
RC =
CK =
CK =
t
t
t
RC (MIN);
CK MIN; CKE = HIGH; Address and other control inputs
CK (MIN); I
PARAMETER/CONDITION
t
RC =
t
t
DD
RC (MIN);
CK =
t
CK =
OUT
Specifications and Conditions – 128MB
= 0mA
t
CK (MIN); DQ, DM, and DQS inputs
t
CK (MIN); DQ, DM and DQS inputs
t
t
RC =
RC =
t
CK =
t
CK =
t
t
RC (MIN);
RAS (MAX);
0.2V
t
IN
t
CK =
CK (MIN); I
t
CK (MIN); CKE = LOW
= V
REF
t
CK (MIN); CKE = (LOW)
t
for DQ, DQS, and DM
CK =
t
CK =
OUT
t
t
REFC =
REFC = 7.8125µs
t
CK (MIN); Address
= 0mA; Address
t
CK (MIN); DQ,
t
RFC (MIN)
T
A
+70°C; V
14
SYMBOL
DD
I
I
I
I
I
I
I
DD4W
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
I
DD3N
I
DD5A
I
I
DD2P
DD3P
DD4R
DD2F
= V
DD0
DD1
DD5
DD6
DD7
DD
Q = +2.5V ±0.2V
64MB, 128MB (x32, SR)
1,020
1,640
500
680
200
120
240
700
700
16
24
16
-6
100-PIN DDR UDIMM
MAX
-75Z/-75
1,460
©2004 Micron Technology, Inc. All rights reserved.
480
620
180
120
200
700
600
980
16
24
16
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28, 45
21, 28, 45
NOTES
20, 43
20, 43
20, 43
20, 45
24, 45
20, 44
46
39
20
9