MT16VDDT12864AY-335F2 Micron Technology Inc, MT16VDDT12864AY-335F2 Datasheet - Page 15

• Manufacturer Part Number: MT16VDDT12864AY-335F2
• Description: MODULE DDR 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT12864AY-335F2

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.44A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13: I
DDR SDRAM Components only
Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
PARAMETER/CONDITION
NOTE:
OPERATING CURRENT: One device bank; Active-Precharge;
t
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 4;
IOUT = 0mA; Address and control inputs changing once per
clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;
(LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;
t
clock cycle; Address and other control inputs changing once
per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once
per clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle;
DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs
(BL = 4) with auto precharge,
(MIN); Address and control inputs change only during Active
READ, or WRITE commands
RC =
CK =
CK =
a: Value calculated as one module rank in this operating condition, and all other module ranks in I
b: Value calculated reflects all module ranks in this operating condition.
t
t
t
RC (MIN);
CK (MIN); DQ, DM andDQS inputs changing twice per
CK MIN; CKE = HIGH; Address and other control
t
t
DD
CK =
CK =
Specifications and Conditions – 512MB
t
t
t
CK (MIN); DQ, DM and DQS inputs
RC =
CK (MIN); IOUT = 0mA
t
RC (MIN);
t
t
RC =
CK =
0.2V
t
t
RC =
CK =
t
CK =
t
t
RC (MIN);
CK (MIN); DQ, DM, and
t
t
t
RAS (MAX);
CK (MIN); CKE =
CK =
t
CK (MIN); CKE =
t
t
REFC =
REFC = 7.8125µs
t
CK (MIN);
t
CK =
t
RFC (MIN)
t
CK
15
256MB, 512MB, 1GB, 2GB (x64, DR)
T
A
I
I
I
I
I
I
I
SYM
DD4W
I
I
DD3N
I
DD5A
I
I
DD2P
DD2F
DD3P
DD4R
DD0
DD1
DD5
DD6
DD7
+70°C; V
b
b
a
a
a
b
b
b
a
b
b
a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
DD
1,032
1,392
1,432
1,432
4,080
3,312
-335
800
480
960
64
96
64
= V
DD
Q = +2.5V ±0.2V
MAX
1,032
1,312
1,232
1,232
3,760
2,832
-262
720
400
800
64
96
64
-26A/
1,192
1,232
1,232
3,760
2,832
-265
992
720
400
800
64
96
64
DD
2p (CKE LOW) mode.
UNITS
©2004 Micron Technology, Inc.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
21, 28,
21, 28,
20, 42
20, 42
20, 42
20, 44
20, 44
20, 43
44
45
44
40
20
9