MT18VDVF12872DG-40BD4 Micron Technology Inc, MT18VDVF12872DG-40BD4 Datasheet - Page 12
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT18VDVF12872DG-40BD4
Manufacturer Part Number
MT18VDVF12872DG-40BD4
Description
MODULE DDR 1GB 184-DIMM VLP
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDVF12872DG-40BD4.pdf
(38 pages)
Specifications of MT18VDVF12872DG-40BD4
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
400MT/s
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Read Latency
Figure 4:
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
Mode Register Definition Diagram
The READ latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first bit of output data. The latency can be set to 2 or 2.5
clocks, as shown in Figure 5, "CAS Latency Diagram," on page 14.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Figure 6, "CAS Latency
Table," on page 13, indicates the operating frequencies at which each CAS latency set-
ting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
0*
14
BA1
0*
13
BA0
12
A12 A11
Operating Mode
11
10
A10
M12 M11
0
0
-
9
A9
0
0
-
8
A8
M10
0
0
-
7
A7 A6 A5 A4 A3
M9
M6
0
0
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
M8 M7
M5
0
1
-
0
0
1
1
0
0
1
1
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
12
M6-M0
M3
0
1
Valid
Valid
3
-
Burst Length
M2
0
0
0
0
1
1
1
1
2
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
2
M0
0
1
0
1
0
1
0
1
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst Type
Interleaved
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 1
2
4
8
Mode Register Definition
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.