MT16VDDF12864HG-40BF2 Micron Technology Inc, MT16VDDF12864HG-40BF2 Datasheet - Page 20

• Manufacturer Part Number: MT16VDDF12864HG-40BF2
• Description: MODULE DDR SDRAM 1GB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDF12864HG-40BF2

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.6A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef80b57837, source: 09005aef80b577fa
DDAF16C64_128x64HG.fm - Rev. D 9/04 EN
39. During Initialization, V
40. The current Micron part operates below the slow-
41. Random addressing changing and 50 percent of
42. Random addressing changing and 100 percent of
43. CKE must be active (high) during the entire time a
160
140
120
100
80
60
40
20
0
Figure 8: Pull-Down Characteristics
0.0
be equal to or less than V
V
even if V
of 42 of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
REF later.
TT
may be 1.35V maximum during power up,
0.5
DD
/V
DD
Q are 0.0V, provided a minimum
1.0
V
V
OUT
OUT
DD
(V)
(V)
DD
Q, V
1.5
+ 0.3V. Alternatively,
TT
, and V
2.0
Minimum
REF
must
TT
2.5
20
44. IDD2N specifies the DQ, DQS, and DM to be
45. Whenever the operating frequency is altered, not
46. Leakage number reflects the worst case leakage
47. When an input signal is HIGH or LOW, it is
48. This is the DC voltage supplied at the DRAM and
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
is inclusive of all noise up to 20MHz. Any noise
above 20MHz at the DRAM generated from any
source other than that of the DRAM itself may not
exceed the DC voltage range of 2.6V ±100mV.
512MB, 1GB (x64, DR) PC3200
Figure 9: Pull-Up Characteristics
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0.5
200-PIN DDR SODIMM
1.0
V
DD
Q - V
OUT
(V)
1.5
©2004 Micron Technology, Inc.
2.0
2.5