MT16HTF12864HY-40EB3 Micron Technology Inc, MT16HTF12864HY-40EB3 Datasheet - Page 7
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MT16HTF12864HY-40EB3
Manufacturer Part Number
MT16HTF12864HY-40EB3
Description
MODULE SDRAM DDR2 1GB 200SODIMM
Manufacturer
Micron Technology Inc
Specifications of MT16HTF12864HY-40EB3
Memory Type
DDR2 SDRAM
Memory Size
1GB
Speed
400MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
128Mx64
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
60ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
976mA
Number Of Elements
16
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
General Description
Serial Presence-Detect EEPROM Operation
PDF: 09005aef818e4054
htf16c128_256x64h.pdf - Rev. D 3/10 EN
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-
mitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
(WP) is connected to V
2
C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
SS
, permanently disabling hardware write protection.
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
General Description
© 2004 Micron Technology, Inc. All rights reserved.