MT18HTF12872AY-53EB1 Micron Technology Inc, MT18HTF12872AY-53EB1 Datasheet - Page 12
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MT18HTF12872AY-53EB1
Manufacturer Part Number
MT18HTF12872AY-53EB1
Description
MODULE SDRAM DDR2 1GB 240DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18HTF12872AY-53EB1.pdf
(18 pages)
Specifications of MT18HTF12872AY-53EB1
Memory Type
DDR2 SDRAM
Memory Size
1GB
Speed
533MT/s
Package / Case
240-DIMM
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240UDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
50ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
1.368A
Number Of Elements
18
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 14:
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. H 5/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
valid commands; Other control and address bus inputs are switching; Data
bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current:
(I
control and address bus inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during DESELECTs; Data bus inputs are switching
RC =
CK =
RAS =
RP =
RAS =
CK =
DD
DD
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
t
t
t
t
t
RP (I
RC (I
RCD =
CK (I
CK (I
t
t
OUT
OUT
RAS MAX (I
RAS MAX (I
DD
= 0mA; BL = 4, CL = CL (I
DD
DD
= 0mA; BL = 4, CL = CL (I
DD
t
); CKE is HIGH, S# is HIGH between valid commands; Address
),
DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
RCD (I
); CKE is LOW; Other control and address
),
t
t
DD
RAS =
RC =
), AL = 0;
Notes:
DD
DD
DD
t
),
),
DD
RC (I
); CKE is HIGH, S# is HIGH between valid commands;
t
RAS MIN (I
t
DD
t
RP =
RP =
t
CK =
Specifications and Conditions (Die Revision E) – 2GB
), AL = 0;
DD
t
1. Value calculated as one module rank in this operating condition and all other module ranks
2. Value calculated reflects all module ranks in this operating condition.
CK =
512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
),
t
t
RP (I
RP (I
t
CK (I
t
in I
RRD =
t
DD
CK (I
DD
DD
DD
DD
t
DD
DD
CK =
); CKE is HIGH, S# is HIGH between
2P (CKE LOW).
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
), AL =
), AL = 0;
); REFRESH command at every
t
DD
RRD (I
),
t
CK (I
t
RC =
t
RCD (I
DD
DD
t
),
CK =
t
RC (I
),
t
t
RCD =
CK =
t
DD
t
RAS =
CK =
t
CK =
t
DD
) - 1 ×
CK (I
t
),
CK (I
t
t
t
RCD (I
OUT
t
CK (I
CK =
t
t
DD
RAS =
DD
t
CK (I
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
RAS MAX (I
CK =
12
t
CK (I
4W
DD
),
= 0mA;
DD
t
),
DD
DD
CK (I
t
t
),
DD
CK (I
RAS MIN
); CKE is
); CKE is
);
t
DD
RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
);
);
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1
1
2
2
1
2
2
1
2
2
2
1
-80E/
1,053
1,080
1,503 1,278 1,188 1,008
1,503 1,278 1,188 1,008
4,230 3,870 3,780 3,690
3,078 2,583 2,493 2,403
-800
873
126
900
900
720
180
126
Electrical Specifications
-667
828
963
126
720
720
540
180
990
126
©2003 Micron Technology, Inc. All rights reserved.
-53E
693
918
126
720
720
540
180
810
126
-40E Units
693
873
126
630
630
540
180
720
126
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA