MT18HTF12872AY-53EB1 Micron Technology Inc, MT18HTF12872AY-53EB1 Datasheet - Page 9

• Manufacturer Part Number: MT18HTF12872AY-53EB1
• Description: MODULE SDRAM DDR2 1GB 240DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18HTF12872AY-53EB1

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 533MT/s
• Package / Case: 240-DIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240UDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 50ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.368A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Table 11:
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. H 5/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
MAX (I
Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
control and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during DESELECTs; Data bus inputs are switching
DD
RC =
RCD =
CK =
RAS =
RP =
CK =
DD
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
Specifications
t
t
t
t
RP (I
RC (I
CK (I
CK (I
DD
t
t
OUT
OUT
RAS MAX (I
RCD (I
DD
),
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
t
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
RP =
); CKE is HIGH, S# is HIGH between valid commands; Address
),
DDR2 I
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus
),
DD
t
t
RAS =
RC =
); CKE is HIGH, S# is HIGH between valid commands; Address
t
RP (I
Notes:
DD
t
t
),
CK =
DD
DD
RC (I
t
RAS MIN (I
t
DD
RP =
); CKE is HIGH, S# is HIGH between valid commands;
t
CK =
Specifications and Conditions – 512MB
), AL = 0;
DD
t
CK (I
1. Value calculated as one module rank in this operating condition and all other module ranks
2. Value calculated reflects all module ranks in this operating condition.
512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
t
),
RP (I
t
CK (I
t
in I
RRD =
DD
DD
DD
DD
),
DD
DD
t
DD
); CKE is HIGH, S# is HIGH between valid
CK =
t
); CKE is HIGH, S# is HIGH between valid
2P (CKE LOW).
RC =
), AL = 0;
), AL =
); REFRESH command at every
t
RRD (I
t
CK (I
t
RC (I
t
DD
RCD (I
DD
t
),
DD
CK =
),
t
t
DD
RCD =
),
CK =
t
t
DD
RAS =
t
CK =
t
4W
RAS =
CK =
t
CK (I
) - 1 ×
t
CK (I
t
t
t
RCD (I
CK =
OUT
CK (I
t
t
DD
t
CK (I
RAS MAX (I
t
CK =
RAS MIN (I
9
t
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
),
CK (I
= 0mA; BL = 4,
DD
t
t
CK (I
),
DD
DD
RAS =
t
),
CK (I
DD
); CKE is
); CKE is
DD
);
t
RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
t
DD
); CKE
DD
RAS
);
),
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1
1
2
2
1
2
2
1
2
2
2
1
Electrical Specifications
1,755
1,665
3,240
2,295
-667
855
945
720
720
540
108
900
90
90
©2003 Micron Technology, Inc. All rights reserved.
1,485
1,395
3,060
2,205
-53E
765
855
630
630
450
108
720
90
90
1,170
1,080
2,970
2,115
-40E
720
810
450
540
360
108
540
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA