MT18VDDF6472DG-40BG2 Micron Technology Inc, MT18VDDF6472DG-40BG2 Datasheet - Page 16

• Manufacturer Part Number: MT18VDDF6472DG-40BG2
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF6472DG-40BG2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 500ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.836A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 13: IDD Specifications and Conditions – 1GB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 4;
I
clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
inputs changing once per clock cycle. V
DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;
t
per clock cycle; Address and other control inputs changing
once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once
per clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle;
and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs
(BL = 4) with auto precharge,
(MIN); Address and control inputs change only during
Active READ, or WRITE commands
RC =
OUT
CK =
CK =
= 0mA; Address and control inputs changing once per
t
t
t
RC (MIN);
CK MIN; CKE = HIGH; Address and other control
CK (MIN); DQ, DM, and DQS inputs changing twice
t
CK =
t
CK =
t
t
RC =
CK (MIN); I
t
CK (MIN); DQ, DM and DQS inputs
t
RC (MIN);
t
RC =
t
t
0.2V
t
CK =
CK =
RC =
t
CK =
OUT
t
RC (MIN);
t
t
= 0mA
CK (MIN); CKE = (LOW)
t
CK (MIN); DQ, DM,
t
RAS (MAX);
t
CK =
CK (MIN); CKE = LOW
IN
t
t
REFC =
REFC = 7.8125µs
= V
t
CK (MIN);
REF
t
CK =
t
for DQ,
RFC (MIN)
t
CK
16
T
SYMBOL
A
I
I
I
I
I
I
I
DD4W
I
I
I
DD3N
DD5A
I
I
DD2P
DD3P
DD4R
DD2F
DD
DD
DD1
DD6
DD7
+70°C; V
0
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
DD
2,340
2,880
2,970
3,150
5,220
7,290
512MB, 1GB (x72, ECC, SR)
-335
810
630
900
180
90
90
= V
DD
Q = +2.5V ±0.2V
MAX
2,340
2,880
2,970
2,790
5,220
7,200
-262
810
630
900
180
90
90
©2004 Micron Technology, Inc. All rights reserved.
-26A/
2,070
2,610
2,610
2,430
5,040
6,300
-265/
-202
720
540
810
180
90
90
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
21, 28,
21, 28,
20, 43
20, 43
20, 43
20, 45
24, 45
20, 44
45
46
45
42
20
9