MT18VDDF6472DG-40BG2 Micron Technology Inc, MT18VDDF6472DG-40BG2 Datasheet - Page 17

• Manufacturer Part Number: MT18VDDF6472DG-40BG2
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF6472DG-40BG2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 500ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.836A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 14: Capacitance
Note: 11; notes appear on pages 21–24
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
PARAMETER
Input/Output Capacitance: DQ, DQS
Input Capacitance: Command and Address, S#, CKE
Input Capacitance: CK, CK#
Operating Conditions (-335, -262)
CL = 2.5
CL = 2
SYMBOL
t
17
t
CK (2.5)
t
DQSCK
t
t
t
t
t
t
T
CK (2)
DQSQ
DQSH
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
MRD
t
t
t
QHS
t
t
DSH
t
t
t
t
RAP
RCD
A
t
t
DSS
IPW
RAS
t
RFC
t
t
t
t
QH
AC
CH
DH
DS
HP
HZ
IH
IH
RC
CL
IS
IS
RP
LZ
F
S
F
S
+70°C; V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
-0.60
-0.70
t
184-PIN DDR SDRAM RDIMM
MIN
t
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.75
0.75
0.80
0.80
-0.7
QHS
HP -
7.5
0.2
0.2
2.2
12
42
15
60
75
15
15
6
t
DD
512MB, 1GB (x72, ECC, SR)
CH,
-335
= V
SYMBOL
70,000
t
+0.60
+0.70
MAX
+0.70
CL
0.55
0.55
0.45
1.25
0.55
DD
13
13
C
C
C
I0
I1
I2
Q = +2.5V ±0.2V
-0.75
t
-0.75
-0.75
t
MIN
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
QHS
HP -
7.5
7.5
0.2
0.2
2.2
15
40
15
60
75
15
15
1
1
t
CH,
-262
©2004 Micron Technology, Inc. All rights reserved.
120,000
t
MIN
CL
MAX
+0.75
+0.75
+0.75
2.5
0.55
0.55
0.50
1.25
0.75
4
2
13
13
MAX
3.5
UNITS
5
3
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNITS
NOTES
40, 46
40, 46
23, 27
23, 27
22, 23
16, 37
16, 37
22, 23
31, 49
pF
pF
pF
26
26
27
30
12
12
12
12
44