MT18VDDT6472AG-335G4 Micron Technology Inc, MT18VDDT6472AG-335G4 Datasheet - Page 9

• Manufacturer Part Number: MT18VDDT6472AG-335G4
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT6472AG-335G4

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.611A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Idd Specifications
Table 9:
PDF: 09005aef80814e61/Source: 09005aef807f8acb
DD18C64_128x72A.fm - Rev. D 9/08 EN
Parameter/Condition
Operating one bank active-precharge current:
DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle; Vin = Vref
for DQ, DQS, and DM
Active power-down standby current: One device bank active; Power-down mode;
t
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
Iout = 0mA
Operating burst write current: BL = 2; Continuous burst writes; One device bank
active; Address and control inputs changing once per clock cycle;
DM, and DQS inputs changing twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving reads
(BL = 4) with auto precharge;
inputs change only during active READ or WRITE commands
CK =
CK =
RC =
t
t
t
CK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle
CK (MIN); CKE = LOW
RAS (MAX);
t
CK =
t
CK (MIN); CKE = LOW
Idd Specifications and Conditions – 512MB (Die Revision K)
Values shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
t
Notes:
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
t
RC =
in Idd2P (CKE LOW) mode.
t
RC (MIN);
512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM
t
CK =
t
RC =
t
CK (MIN); Address and control
t
RC (MIN);
t
CK =
9
t
t
REFC =
REFC = 15.625µs
t
t
CK (MIN);
t
RC =
t
CK =
CK =
t
CK =
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RFC (MIN)
t
t
RC (MIN);
t
CK (MIN); DQ,
CK (MIN);
t
CK (MIN);
Symbol
Idd4W
Idd3N
Idd5A
Idd4R
Idd2P
Idd2F
Idd3P
Idd0
Idd1
Idd5
Idd6
Idd7
Electrical Specifications
1
1
2
2
1
2
2
2
1
2
2
1
©2004 Micron Technology, Inc. All rights reserved
1,116
1,080
1,656
1,656
2,880
2,646
-40B
936
900
630
72
72
36
1,071
1,476
1,476
2,880
2,466
-335
846
900
540
990
72
72
36
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA