MT36VDDF12872G-265G3 Micron Technology Inc, MT36VDDF12872G-265G3 Datasheet - Page 13

• Manufacturer Part Number: MT36VDDF12872G-265G3
• Description: MODULE SDRAM DDR 1GB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36VDDF12872G-265G3

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 2.772A
• Number Of Elements: 36
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 10:
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge;
and control inputs change only during active READ or WRITE commands
CK =
RC =
RC =
CK =
IN
= V
t
t
t
t
t
RC (MIN);
RAS (MAX);
CK (MIN); DQ and DQS inputs changing once per clock cycle; Address
CK (MIN); I
CK =
REF
for DQ and DQS
t
CK (MIN); DQ and DQS inputs changing twice per clock cycle
t
t
I
Values are for the MT46V64M4 DDR SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
CK =
CK =
DD
t
CK =
OUT
Specifications and Conditions – 1GB (All Other Die Revisions)
t
t
t
Notes:
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
= 0mA
t
CK (MIN); I
t
CK (MIN); DQ and DQS inputs changing twice per
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
in I
OUT
DD
t
RC =
2P (CKE LOW) mode.
= 0mA; Address and control inputs
t
RC (MIN);
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
t
t
RC =
CK =
t
t
RFC =
RFC = 7.8125µs
t
t
RC (MIN);
t
CK (MIN); Address
CK =
13
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol -40B
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
2,502 2,322 2,322 2,232
3,132 3,132 2,952 2,682
2,160 1,800 1,620 1,620
1,440 1,080
2,520 2,160 1,800 1,800
3,672 3,222 2,772 2,772
3,582 3,222 2,772 2,772
9,360 9,180 8,460 8,460/
8,532 7,452 6,372 6,372/
144
216
144
Electrical Specifications
-335
©2002 Micron Technology, Inc. All rights reserved.
144
216
144
-262
144
900
216
144
-26A/
1,080
8,820
6,642
-265
900/
144
216
144
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA