MT4VDDT864AG-265B1 Micron Technology Inc, MT4VDDT864AG-265B1 Datasheet - Page 4

• Manufacturer Part Number: MT4VDDT864AG-265B1
• Description: MODULE SDRAM DDR 64MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT864AG-265B1

• Memory Type: DDR SDRAM
• Memory Size: 64MB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5:
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
pdf: 09005aef8085081a, source: 09005aef806e129d
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
184-Pin DIMM Pinouts
16, 17, 75, 76, 137, 138
PIN NUMBERS
63, 65, 154
52, 59
157
21
Pin Descriptions
Back View
Front View
PIN 1
PIN 184
U1
WE#, CAS#,
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
SYMBOL
BA0, BA1
RAS#
CKE
S0#
No Components This Side of Module
Indicates a V
U2
PIN 145
TYPE
Input
Input
Input
Input
Input
DD
or V
PIN 52
DDQ
4
PIN 144
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK and CK# are differential clock inputs. All address
and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers, and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE
POWER-DOWN (row ACTIVE in any device bank). CKE is
synchronous for POWER-DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit
and for disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V
CKE is brought HIGH, it becomes an SSTL_2 input only.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
pin
64MB, 128MB, 256MB (x64, SR)
DD
Indicates a V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PIN 53
184-PIN DDR SDRAM UDIMM
is applied and until CKE is first brought HIGH. After
U4
SS
pin
DESCRIPTION
U5
PIN 92
PIN 93
U6
©2004 Micron Technology, Inc.