MT4VDDT864AG-265B1 Micron Technology Inc, MT4VDDT864AG-265B1 Datasheet - Page 9

• Manufacturer Part Number: MT4VDDT864AG-265B1
• Description: MODULE SDRAM DDR 64MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT864AG-265B1

• Memory Type: DDR SDRAM
• Memory Size: 64MB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
NOTE:
Table 7:
pdf: 09005aef8085081a, source: 09005aef806e129d
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
1. For a burst length of two, A1
2. For a burst length of four, A2
3. For a burst length of eight, A3
4. Whenever a boundary of the block is reached within a
5. Ai = A8 (64MB, 128MB)
LENGTH
BURST
element block; A0 selects the first access within the
block.
element block; A0-A1 select the first access within the
block.
element block; A0
block.
given sequence above, the following access wraps
within the block.
Ai = A9 (256MB).
SPEED
2
4
8
-26A
-335
-262
-265
A2 A1 A0
STARTING
ADDRESS
0
0
0
0
1
1
1
1
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
–
A0
A2 select the first access within the
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 100
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLOCK FREQUENCY (MHZ)
ALLOWABLE OPERATING
CL = 2
ORDER OF ACCESSES WITHIN
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
SEQUENTIAL
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
–
0-1
1-0
–
Ai select the two-data-
Ai select the four-data-
–
Ai select the eight-data-
A BURST
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
75 ≤ f ≤ 167
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
CL = 2.5
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
9
Operating Mode
MODE REGISTER SET command with bits A7–A11
(64MB) or A7–A12 (128MB, 256MB) each set to zero,
and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A11 (64MB) or A9–A12 (128MB,
256MB) each set to zero, bit A8 set to one, and bits A0–
A6 set to the desired values. Although not required by
the Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
or A7–A12 (128MB, 256MB) are reserved for future use
and/or test modes. Test modes and reserved states
should not be used because unknown operation or
incompatibility with future versions may result.
Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown inFigure 5, Extended Mode Register
Definition Diagram, on page 10. The extended mode
register is programmed via the LOAD MODE REGIS-
COMMAND
COMMAND
64MB, 128MB, 256MB (x64, SR)
The normal operating mode is selected by issuing a
All other combinations of values for A7–A11 (64MB)
The extended mode register controls functions
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 4: CAS Latency Diagram
CK
CK
184-PIN DDR SDRAM UDIMM
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
T2
NOP
NOP
T2
©2004 Micron Technology, Inc.
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n