MT9HTF12872AY-40ED1 Micron Technology Inc, MT9HTF12872AY-40ED1 Datasheet - Page 38
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MT9HTF12872AY-40ED1
Manufacturer Part Number
MT9HTF12872AY-40ED1
Description
MODULE SDRAM DDR2 1GB 240DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9HTF12872AY-40ED1.pdf
(44 pages)
Specifications of MT9HTF12872AY-40ED1
Memory Type
DDR2 SDRAM
Memory Size
1GB
Speed
400MT/s
Package / Case
240-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Serial Presence-Detect
SPD Clock and Data Conventions
SPD Start Condition
SPD Stop Condition
SPD Acknowledge
Figure 12:
pdf: 09005aef80e6f860, source: 09005aef80e5b799
HTF9C32_64_128x72AG_2.fm - Rev. C 6/05 EN
Data Validity
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (Figure 12, Data Validity,
and Figure 13, Definition of Start and Stop).
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-
sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 14, Acknowledge Response From Receiver).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each sub-
sequent eight-bit word. In the read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
SDA
SCL
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 SDRAM UDIMM
DATA STABLE
DATA
CHANGE
38
DATA STABLE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
Serial Presence-Detect