MT36HTS51272FY-53EA3E3 Micron Technology Inc, MT36HTS51272FY-53EA3E3 Datasheet - Page 9

• Manufacturer Part Number: MT36HTS51272FY-53EA3E3
• Description: MODULE DDR2 4GB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS51272FY-53EA3E3

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 533MT/s
• Package / Case: 240-FBDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Advanced Memory Buffer (AMB)
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
The AMB reference design complies with the JEDEC standard, “FBDIMM Architecture
and Protocol Specification.” It is expected that there will be AMB multiple vendors,
which will offer at least the minimum functionality set forth in the industry specifica-
tion. To achieve optimal operation and compatibility with DDR2 SDRAM device and
host/controller offerings, each vendor’s AMB will have a unique set of personality bytes
contained in the SPD for setting up and fine tuning that device.
The FBDIMM specification defines a number of options to support the requirements of
different applications. The capabilities of the AMB are communicated to the host during
the initialization process in the TS2 training pattern and in bits readable in the features
register in the AMB.
The AMB is responsible for handling FBDIMM channel and memory requests to and
from the local FBDIMM and for forwarding requests to other FBDIMMs on the channel.
A complete and detailed description of the AMB is contained in the proposed FBDIMM
AMB Specification. The AMB is a memory interface that connects an array of DDR2
SDRAM devices to the FBDIMM channel. The AMB is a slave device on the channel
responding to channel commands and forwarding channel commands to other AMB
devices.
All memory control for the DDR2 SDRAM resides in the host, including memory request
initiation, timing, refresh, scrubbing, sparing, configuration access, and power manage-
ment.
The AMB is expected to perform the following functions:
• Support channel initialization procedures as defined in the initialization chapter of
• Support the forwarding of southbound and northbound frames, servicing requests
• Initialize northbound frames if the FBDIMM’s AMB is the last, southern-most frame
• Detect errors on the channel and report them to the host memory controller
• Support the FBDIMM configuration register set as defined in the FBDIMM AMB spec-
• Act as a DRAM memory buffer for all read, write, and configuration accesses
• Provide a read and write buffer FIFO
• Support an SMBus protocol interface for access to the AMB configuration registers
• Provide features to support MEMBIST and IBIST test functions
• Provide a register interface for the thermal sensor and status indicator
• Function as a repeater to extend the maximum length of FBDIMM Links
• Reconfigure FBDIMM inputs from differential high-speed link receivers to two single-
• Bypass high speed parallel/serial circuitry and provide test results back to the tester,
the FBDIMM Architecture and Protocol Specification to align the clocks and the
frame boundaries and verify channel connectivity
directed to a specific FBDIMM’s AMB, as defined in the protocol chapter of the speci-
fication, and merging the return data into the northbound frames
on the channel
ification register chapter of the specification
addressed to a specific FBDIMM’s AMB
ended, low-speed receivers (~200 MHz). These inputs directly control DDR2
command/address and input data that replicates to all DDR2 SDRAM devices.
using low-speed FBDIMM outputs.
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
©2006 Micron Technology, Inc. All rights reserved.
Preliminary