MT4VDDT1664HY-335F3 Micron Technology Inc, MT4VDDT1664HY-335F3 Datasheet - Page 26
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MT4VDDT1664HY-335F3
Manufacturer Part Number
MT4VDDT1664HY-335F3
Description
MODULE DDR 128MB 200-SODIMM
Manufacturer
Micron Technology Inc
Specifications of MT4VDDT1664HY-335F3
Memory Type
DDR SDRAM
Memory Size
128MB
Speed
200MHz
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
16Mx64
Total Density
128MByte
Chip Density
256Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
880mA
Number Of Elements
4
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1344
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
pdf: 09005aef8086ea3d, source: 09005aef8086ea0b
DD4C8_16_32x64HG.fm - Rev. C 9/04 EN
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT: SCL = SDA = V
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
of SDA.
EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
OUT
SS
SS
IN
; V
; V
= 3mA
OUT
= GND to V
DDSPD
DDSPD
= GND to V
DD
- 0.3V; All other inputs = V
= +2.3V to +3.6V
= +2.3V to +3.6V
t
WRC) is the time from a valid stop condition of a write sequence to the end of the
DD
DD
26
SS
or V
64MB, 128MB, 256MB (x64, SR)
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
t
HIGH
LOW
f
WRC
SYMBOL
t
t
BUF
SCL
AA
DH
t
t
V
t
F
R
I
DDSPD
V
V
V
I
I
I
I
LO
SB
CC
OL
LI
IH
IL
V
MIN
DDSPD
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
MIN
2.3
-1
–
–
–
–
–
MAX
©2004 Micron Technology, Inc. All rights reserved.
300
400
0.7
0.9
0.3
50
10
V
V
DDSPD
DDSPD
UNITS
KHz
MAX
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
3.6
0.4
10
10
30
2
+ 0.5
0.3
NOTES
UNITS
1
2
2
3
4
mA
µA
µA
µA
V
V
V
V