MT9HTF6472RHY-667D1 Micron Technology Inc, MT9HTF6472RHY-667D1 Datasheet - Page 22

MODULE DDR2 512MB 200-SORDIMM

MT9HTF6472RHY-667D1

Manufacturer Part Number
MT9HTF6472RHY-667D1
Description
MODULE DDR2 512MB 200-SORDIMM
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT9HTF6472RHY-667D1

Memory Type
DDR2 SDRAM
Memory Size
512MB
Speed
667MT/s
Package / Case
200-SORDIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Quantity
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Part Number:
MT9HTF6472RHY-667D1
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Quantity:
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Temperature Trip Point Registers
Table 24: Alarm Temperature Lower Boundary Register (Address: 0x02)
Table 25: Alarm Temperature Lower Boundary Register (Address: 0x03)
Critical Temperature Register
Table 26: Critical Temperature Register (Address: 0x04)
Temperature Register
PDF: 09005aef828742dd
htf9c64_128x72rh.pdf - Rev. D 3/10 EN
15
15
15
0
0
0
14
14
14
0
0
0
13
13
13
0
0
0
MSB
MSB
MSB
12
12
12
The upper and lower temperature boundary registers are used to set the maximum and
minimum values of the alarm window. LSB for these registers is 0.25°C. All RFU bits in
the register will always report zero.
The critical temperature register is used to set the maximum temperature above the
alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always
report zero.
The temperature register is a read-only register that provides the current temperature
detected by the temperature sensor. The LSB for this register is 0.0625°C with a resolu-
tion of 0.0625°C. The most significant bit (MSB) is 128°C in the readout section of this
register.
The upper three bits of the register are used to monitor the trip points that are set in the
previous three registers.
11
11
11
512MB, 1GB (x72, ECC, SR) 200-Pin DDR2 SDRAM SORDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
10
10
10
Alarm window upper boundary temperature
Alarm window lower boundary temperature
9
9
9
Critical temperature trip point
8
8
8
Bit
Bit
Bit
22
7
7
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
6
6
6
5
5
5
4
4
4
© 2007 Micron Technology, Inc. All rights reserved.
3
3
3
LSB
LSB
LSB
2
2
2
RFU
RFU
RFU
1
1
1
RFU
RFU
RFU
0
0
0

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