AFCT-5962ATLZ Avago Technologies US Inc., AFCT-5962ATLZ Datasheet - Page 2

• Manufacturer Part Number: AFCT-5962ATLZ
• Description: TXRX OPT SM SONET OC3/SDH 2X10
• Manufacturer: Avago Technologies US Inc.
• Series: METRAKr

Specifications of AFCT-5962ATLZ

• Applications: General Purpose
• Connector Type: LC Duplex
• Data Rate: 155Mbps
• Wavelength: 1300nm
• Voltage - Supply: 3.1 V ~ 3.5 V
• Mounting Type: Through Hole
• Data Rate Max: 0.155Gbps
• Supply Voltage: 3.3V
• Wavelength Typ: 1300nm
• Leaded Process Compatible: Yes
• Optical Fiber Type: TX/RX
• Data Transfer Rate: 155Mbps
• Optical Rise Time: 2/2.2ns
• Optical Fall Time: 2/2.2ns
• Operating Temperature Classification: Industrial
• Peak Wavelength: 1360/1580nm
• Package Type: DIP With Connector
• Operating Supply Voltage (min): 3.1V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.5V
• Output Current: 50mA
• Operating Temp Range: -40C to 85C
• Mounting: Snap Fit To Panel
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Functional Description
Receiver Section
Design
The receiver section for the AFCT-5962TLZ/
TGZ/ATLZ/ATGZ/NLZ/NGZ contains an InGaAs/
InP photo detector and a preamplifier mounted
in an optical subassembly. This optical
subassembly is coupled to a postamp/decision
circuit on a circuit board. The design of the
optical assembly is such that it provides better
than 14 dB Optical Return Loss (ORL).
The postamplifier is ac coupled to the preamplifier
as illustrated in Figure 1. The coupling capacitors
are large enough to pass the SONET/SDH test
pattern at 155 Mb/s without significant distortion
or performance penalty. If a lower signal rate,
or a code which has significantly more low
frequency content is used, sensitivity, jitter and
pulse distortion could be degraded.
Figure 1 also shows a filter function which
limits the bandwidth of the preamp output
signal. The filter is designed to bandlimit the
preamp output noise and thus improve the
receiver sensitivity.
Figure 1. Receiver Block Diagram
2
PHOTODETECTOR
BIAS
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
GND
FILTER
AMPLIFIER
CIRCUIT
SIGNAL
DETECT
These components will reduce the sensitivity of
the receiver as the signal bit rate is increased
above 155 Mb/s.
The device incorporates a photodetector bias
circuit. This output must be connected to V
and can be monitored by connecting through a
series resistor (see Application Section).
Noise Immunity
The receiver includes internal circuit components
to filter power supply noise.
some conditions of EMI and power supply noise,
external power supply filtering may be necessary
(see Application Section).
The Signal Detect Circuit
The signal detect circuit works by sensing the
level of the received signal and comparing this
level to a reference. The SD output is low
voltage PECL.
LVPECL
OUTPUT
BUFFER
LVPECL
OUTPUT
BUFFER
DATA OUT
DATA OUT
SD
However under
CC