HW-FLYLEADS Xilinx Inc, HW-FLYLEADS Datasheet - Page 16

• Manufacturer Part Number: HW-FLYLEADS
• Description: LEAD WIRES FLYING CABLE III/IV
• Manufacturer: Xilinx Inc

Specifications of HW-FLYLEADS

• Accessory Type: Parallel Cable
• For Use With/related Products: Xilinx FPGA, CPLDS, Platform Flash PROMs, XC18V00 PROMs, System ACE MPM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1473

Interface Pin Descriptions
Table 5: SS/JTAG/SPI Port: 14-Pin Ribbon Cable Connector
DS300 (v3.2) May 14, 2008
Product Specification
Number
Ribbon
Cable
10
12
14
10
10
2
4
6
8
4
6
8
8
6
4
Configuration
Slave-Serial
R
PROG
DONE
CCLK
Mode
V
INIT
DIN
N/C
REF
–
–
–
–
–
–
–
–
Configuration
Mode
JTAG
V
TMS
TCK
TDO
N/C
TDI
REF
–
–
–
–
–
–
–
–
–
Programming
SPI
Mode
MOSI
MISO
SCK
SS
–
–
–
–
–
–
–
–
–
–
–
(2)
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BIDIR
Type
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
–
Target Reference Voltage.
voltage bus on the target system that serves the JTAG, slave-serial
interface. or SPI. For example, when programming a Coolrunner-II
device using the JTAG port, V
V
Configuration Reset. This pin is used to force a reconfiguration of
the target FPGA(s). It should be connected to the PROG_B pin of
the target FPGA for a single-device system, or to the PROG_B pin
of all FPGAs in parallel in a daisy-chain configuration.
Configuration Clock. FPGAs load one configuration bit per CCLK
cycle in slave-serial mode. CCLK should be connected to the CCLK
pin on the target FPGA for a single-device configuration, or to the
CCLK pin of all FPGAs in parallel in a daisy-chain configuration.
Configuration Done. This pin indicates to Platform Cable USB
that target FPGAs have received the entire configuration bitstream.
It should be connected to the Done pin on all FPGAs in parallel for
daisy-chained configurations. Additional CCLK cycles are issued
following the positive transition of Done to insure that the
configuration process is complete.
Configuration Data Input. This is the serial input data stream for
target FPGAs. It should be connected to the DIN pin of the target
FPGA in a single-device system, or to the DIN pin of the first FPGA
in a daisy-chain configuration.
Reserved. This pin is reserved for Xilinx diagnostics and should
not be connected to any target circuitry.
Configuration Initialize. This pin indicates that configuration
memory is being cleared. It should be connected to the INIT_B pin
of the target FPGA for a single-device system, or to the INIT_B pin
on all FPGAs in parallel in a daisy-chain configuration.
Test Mode Select. This is the JTAG mode signal that establishes
appropriate TAP state transitions for target ISP devices. It should
be connected to the TMS pin on all target ISP devices that share
the same data stream.
Test Clock. This is the clock signal for JTAG operations, and
should be connected to the TCK pin on all target ISP devices that
share the same data stream.
Test Data Out. This is the serial data stream received from the
TDO pin on the last device in a JTAG chain.
Test Data In. This is the serial data stream transmitted to the TDI
pin on the first device in a JTAG chain.
SPI Master-Output Slave-Input. This pin is the target serial input
data stream for SPI operations and should be connected to the D
pin on the SPI flash PROM.
SPI Master-Input, Slave-Output. This pin is the target serial
output data stream for SPI operations and should be connected to
the Q
SPI Clock. This pin is the clock signal for SPI operations and
should be connected to the C
SPI Select. This pin is the active-Low SPI chip select signal. This
should be connected to the S
AUX
(2)
bus.
pin on the SPI flash PROM.
Description
(3)
REF
(2)
(2)
This pin should be connected to a
pin on the SPI flash PROM.
pin on the SPI flash PROM.
should be connected to the target
Platform Cable USB
(2)
16