C8051T610DB24 Silicon Laboratories Inc, C8051T610DB24 Datasheet - Page 42
![DAUGHTER BOARD T610 24QFN SOCKET](/photos/9/2/90276/c8051t610db24_sml.jpg)
C8051T610DB24
Manufacturer Part Number
C8051T610DB24
Description
DAUGHTER BOARD T610 24QFN SOCKET
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051T610DB32.pdf
(218 pages)
Specifications of C8051T610DB24
Module/board Type
Socket Module - QFN
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610DK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1507
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C8051T610/1/2/3/4/5/6/7
8.3.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in delayed track-
ing mode, three SAR clocks are used for tracking at the start of every conversion. For many applications,
these three SAR clocks will meet the minimum tracking time requirements.
Figure 8.3 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 8.1. See Table 7.8 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
42
TOTAL
is the sum of the AMUX0 resistance and any external source resistance.
Note: See electrical specification tables for R
Input Pin
Equation 8.1. ADC0 Settling Time Requirements
Figure 8.3. ADC0 Equivalent Input Circuits
t
=
RC
MUX Select
ln
Input
------ -
SA
= R
2
n
MUX
* C
R
Rev 1.0
R
TOTAL
SAMPLE
MUX
C
SAMPLE
MUX
and C
C
SAMPLE
SAMPLE
parameters.
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